Datasheet

Table Of Contents

TMS320DM6467T

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SPRS605C –JULY 2009–REVISED JUNE 2012

7.24.2 UART Peripheral Register Description(s)

Table 7-124 shows the UART register name summary. Table 7-125, Table 7-126, and Table 7-127 show

the UART0/1/2 registers, respectively along with their configuration requirements.

Table 7-124. UART Register Summary

ACRONYM REGISTER NAME ACRONYM REGISTER NAME

RHR Receive Holding Register RXFLH Receive Frame Length High Register

THR Transmit Holding Register BLR BOF Control Register

IER Interrupt Enable Register ACREG Auxilliary Control Register

IIR Interrupt Identification Register SCR Supplementary Control Register

FCR FIFO Control Register SSR Supplementary Status Register

LCR Line Control Register EBLR BOF Length Register

MCR Modem Control Register MVR Module Version Register

LSR Line Status Register SYSC System Configuration Register

MSR Modem Status Register SYSS System Status Register

SPR Scratchpad Register WER Wake-up Enable Register

TCR Transmission Control Register CFPS Carrier Frequency Prescaler Register

TLR Trigger Level Register DLL Divisor Latch Low Register

MDR1 Mode Definition Register 1 DLH Divisor Latch High Register

MDR2 Mode Definition Register 2 UASR UART Autobauding Status Register

SFLSR Status FIFO Line Status Register EFR Enhanced Feature Register

RESUME Resume Register XON1 UART XON1 Character Register

SFREGL Status FIFO Register Low XON2 UART XON2 Character Register

SFREGH Status FIFO Register High XOFF1 UART XOFF1 Character Register

TXFLL Transmit Frame Length Low Register XOFF2 UART XOFF2 Character Register

TXFLH Transmit Frame Length High Register ADDR1 IrDA Address 1 Register

RXFLL Receive Frame Length Low Register ADDR2 IrDA Address 2 Register

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