Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 3-6. Oscillator/PLL Terminal Functions
SIGNAL
TYPE
(1)
OTHER
(2)
DESCRIPTION
NAME NO.
OSCILLATOR, PLL
Crystal input DEV_MXI for DEV oscillator (system oscillator, between 27 MHz and
DEV_MXI/
B15 I DEV_DV
DD18
35 MHz, typically 33 MHz or 33.3 MHz). If the internal oscillator is bypassed, this pin
DEV_CLKIN
is the 1.8-V external oscillator clock input.
Crystal output for DEV oscillator. If the internal oscillator is bypassed, DEV_MXO
DEV_MXO A15 O DEV_DV
DD18
should be left as a No Connect.
1.8-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_DV
DD18
D15 S
(3)
DEV_DV
DD18
should still be connected to the 1.8-V power supply.
I/O ground for DEV oscillator. If the internal oscillator is bypassed, DEV_DV
SS
DEV_DV
SS
E14 GND
(3)
should be connected to ground V
SS
.
1.3-V power supply for DEV oscillator. If the internal oscillator is bypassed,
DEV_CV
DD
E15 S
(3)
DEV_CV
DD
should be connected to the 1.3-V power supply (CV
DD
).
Ground for DEV oscillator. Connect to crystal load capacitors. Do not connect to
DEV_V
SS
C15 GND
(3)
board ground (V
SS
). If the internal oscillator is bypassed, DEV_V
SS
should still be
connected to ground V
SS
.
Crystal input for Auxiliary (AUX) oscillator (24/48 MHz for USB, and UART2/1/0 and
AUX_MXI/ McASP1/0). If the internal oscillator is bypassed, this pin is the 1.8-V external
B17 I AUX_DV
DD18
AUX_CLKIN oscillator clock input. When the peripheral is not used, AUX_MXI should be left as a
No Connect.
Crystal output for AUX oscillator. If the internal oscillator is bypassed, AUX_MXO
AUX_MXO A17 O AUX_DV
DD18
should be left as a No Connect. When the peripheral is not used, AUX_MXO should
be left as a No Connect.
1.8-V power supply for AUX oscillator. If the internal oscillator is bypassed,
AUX_DV
DD18
should still be connected to the 1.8-V power supply. When the
AUX_DV
DD18
D16 S
(3)
peripheral is not used, AUX_DV
DD18
should be connected to the 1.8-V power
supply.
I/O ground for AUX oscillator. If the internal oscillator is bypassed, AUX_DV
SS
AUX_DV
SS
C16 GND
(3)
should be connected to ground (V
SS
). When the peripheral is not used, AUX_DV
SS
should be connected to ground (V
SS
).
1.3-V power supply for AUX oscillator. If the internal oscillator is bypassed,
AUX_CV
DD
should be connected to the 1.3-V power supply (CV
DD
). When the
AUX_CV
DD
E16 S
(3)
peripheral is not used, AUX_CV
DD
should be connected to the 1.3-V power supply
(CV
DD
).
Ground for AUX oscillator. Connect to crystal load capacitors. Do not connect to
board ground (V
SS
). If the internal oscillator is bypassed, AUX_V
SS
should still be
AUX_V
SS
C17 GND
(3)
connected to ground (V
SS
). When the peripheral is not used, AUX_V
SS
should be
connected to ground (V
SS
).
PLL1V
DD18
B14
S
(3)
1.8-V power supply for PLLs.
PLL2V
DD18
B16
PLL1V
SS
C14
GND
(3)
Ground for PLLs.
PLL2V
SS
A16
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
(3) For more information, see the Recommended Operating Conditions table
32 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated
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