Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-113. General Input Timing Requirements in Slave Mode
(1)
-1G
NO. UNIT
MIN MAX
9 t
c(CLK)
Cycle time, SPI_CLK 2P ns
10 t
w(CLKH)
Pulse width, SPI_CLK high P ns
11 t
w(CLKL)
Pulse width, SPI_CLK low P ns
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode, 2P
polarity = 0, phase = 0
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode, 2P
polarity = 0, phase = 1
15 t
su(SIMO-CLK)
ns
Setup time, SPI_SIMO data valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode, 2P
polarity = 1, phase = 0
Setup time, SPI_SIMO data valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode, 2P
polarity = 1, phase = 1
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode, 2
polarity = 0, phase = 0
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode, 2
polarity = 0, phase = 1
16 t
h(CLK-SIMO)
ns
Hold time, SPI_SIMO data valid after receive rising edge of
SPI_CLK, 3-/4-/5-pin mode, 2
polarity = 1, phase = 0
Hold time, SPI_SIMO data valid after receive falling edge of
SPI_CLK, 3-/4-/5-pin mode, 2
polarity = 1, phase = 1
(1) P = period of SPI core clock
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