Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.20.3.2 ATA Multiword DMA Timing
Table 7-91. Timings for ATA Module — Multiword DMA AC Timing
(1) (2)
(see Figure 7-65)
-1G
NO. UNIT
MODE MIN MAX
1 t
0
Cycle time 0-2 (DMASTB + DMARCVR + 2)P - 0.5 ns
2 t
D
DIOW/DIOR active low pulse duration 0-2 (DMASTB + 1)P - 1 ns
0 150 ns
DIOR data access, DIOR falling edge to DD[15:0]
3 t
E
1 60 ns
valid
2 50 ns
DIOR data hold time, DD[15:0] valid after DIOR
4 t
F
0-2 5 ns
rising edge
DIOW/DIOR data setup time, DD[15:0] (OUT) valid
0-2 (DMASTB)P ns
before DIOW/DIOR rising edge
0 100 ns
5 t
G
DIOW/DIOR data setup time, DD[15:0] (IN) valid
1 30 ns
before DIOW/DIOR rising edge
2 20 ns
DIOW data hold time, DD[15:0] valid after DIOW
6 t
H
0-2 (HWNHLD + 1)P + 1 ns
rising edge
7 t
I
DMACK to DIOW/DIOR setup 0-2 (DMARCVR + 1)P - 1.7 ns
8 t
J
DIOW/DIOR to DMACK hold 0-2 5P - 5.9 ns
9 t
KR
DIOR negated pulse width 0-2 (DMARCVR + 1)P - 1 ns
10 t
KW
DIOW negated pulse width 0-2 (DMARCVR + 1)P - 1 ns
0 120 ns
11 t
LR
DIOR to DMARQ delay 1 45 ns
2 35 ns
0-1 40 ns
12 t
LW
DIOW to DMARQ delay
2 35 ns
13 t
M
ATA_CSx valid to DIOW/DIOR setup 0-2 (DATRCVR)P - 1.7 ns
14 t
N
ATA_CSx valid after DIOW/DIOR rising edge hold 0-2 5P - 1.7 ns
0 20 ns
15 t
Z
DMACK to read data (DD[15:0]) released
1-2 25 ns
(1) P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2) DMASTB equals the value programmed in the DMASTBxP bit field in the DMASTB register. DMARCVR equals the value programmed
in the DMARCVRxP bit field in the DMARCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
SPRUEQ3).
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