Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information

TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
7.20.3 ATA Electrical Data/Timing
All ATA AC timing data described in Section 7.20.3.1 – Section 7.20.3.3 is provided at the DM6467T
device pins. For more details, see Section 7.1, Parameter Information.
The AC timing specifications described in Section 7.20.3.1 – Section 7.20.3.3 assume correct
configuration of the ATA memory-mapped control registers for the selected ATA frequency of operation.
7.20.3.1 ATA PIO Data Transfer AC Timing
Table 7-90. Timings for ATA Module — PIO Data Transfer
(1) (2)
(see Figure 7-64)
-1G
NO. UNIT
MODE MIN MAX
1 t
0
Cycle time 0-4
(3)
(DATSTB + DATRCVR + 2)P -0.5 ns
2 t
1
Address valid to DIOW/DIOR setup 0-4
(3)
12P - 1.6 ns
3 t
2
DIOW/DIOR pulse duration low 0-4
(3)
(DATSTB + 1)P - 1
ns
0-2 – ns
4 t
2i
DIOW/DIOR recovery time, pulse duration high
3-4
(3)
(DATRCVR + 1)P - 1 ns
DIOW data setup time, DD[15:0] valid before
5 t
3
0-4
(3)
(DATSTB + 1)P ns
DIOW rising edge
DIOW data hold time, DD[15:0] valid after DIOW
6 t
4
0-4
(3)
(HWNHLD + 1)P + 1 ns
rising edge
0 50 ns
DIOR data setup time, DD[15:0] valid before DIOR
7 t
5
1 35 ns
rising edge
2-4
(3)
20 ns
DIOR data hold time, DD[15:0] valid after DIOR
8 t
6
0-4
(3)
5 ns
rising edge
Output data 3-state, DD[15:0] 3-state after DIOR
9 t
6Z
0-4
(3)
30 ns
rising edge
10 t
9
DIOW/DIOR to address valid hold 0-4
(3)
(HWNHLD + 1)P - 2.1 ns
Read data setup time, DD[15:0] valid before
11 t
RD
0-4
(3)
0 ns
IORDY active
12 t
A
IORDY setup 0-4
(3) (4)
35 ns
13 t
B
IORDY pulse width 0-4
(3)
1250 ns
14 t
C
IORDY assertion to release 0-4
(3)
5 ns
(1) P = SYSCLK4 period, in ns, for ATA. For example, when running the DSP CPU at 1 GHz, use P = 7 ns.
(2) DATSTB equals the value programmed in the DATSTBxP bit field in the DATSTB register. DATRCVR equals the value programmed in
the DATRCVRxP bit field in the DATRCVR register. HWNHLD equals the value programmed in the HWNHLDxP bit field in the
MISCCTL register. For more detailed information, see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number
SPRUEQ3).
(3) The sustained throughput for PIO modes 3 and 4 is limited to the throughput equivalent of PIO mode 2. For more detailed information,
see the TMS320DM646x DMSoC ATA Controller User's Guide (literature number SPRUEQ3).
(4) The t
A
parameter must be met only when the IORDY timer is enabled to allow a device to insert wait states during a transaction. In order
to meet the t
A
parameter, a minimum frequency for SYSCLK4 is specified for each PIO as follows:
• PIO mode 0, MIN frequency = 15 MHz
• PIO mode 1, MIN frequency = 22 MHz
• PIO mode 2, MIN frequency = 31 MHz
• PIO mode 3, MIN frequency = 45 MHz
• PIO mode 4, MIN frequency = 57 MHz
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