Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 7-86. USB2.0 Registers (continued)
HEX ADDRESS
ACRONYM REGISTER NAME
RANGE
Port of the hub that has to be accessed through the associated RX Endpoint.
0x01C6 44A7 RXHUBPORT This is used only when full-speed or low-speed device is connected via a USB2.0
high-speed hub.
Control and Status Register for Endpoint 0 - EOCSR0
PERI_CSR0 Control Status Register for Endpoint 0 in Peripheral mode
0x01C6 4502
HOST_CSR0 Control Status Register for Endpoint 0 in Host mode
0x01C6 4508 COUNT0 Number of Received Bytes in Endpoint 0 FIFO
0x01C6 450A HOST_TYPE0 Defines the Speed of Endpoint 0
0x01C6 450B HOST_NAKLIMIT0 Sets the NAK response timeout on Endpoint 0.
0x01C6 450F CONFIGDATA Returns details of core configuration
Control and Status Register for Endpoint 1 - EOCSR1
0x01C6 4510 TXMAXP Maximum Packet size for Peripheral/Host TX Endpoint
PERI_TXCSR Control Status Register for Peripheral TX Endpoint
0x01C6 4512
HOST_TXCSR Control Status Register for Host TX Endpoint
0x01C6 4514 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint
PERI_RXCSR Control Status Register for Peripheral RX Endpoint
0x01C6 4516
HOST_RXCSR Control Status Register for Host RX Endpoint
0x01C6 4518 RXCOUNT Number of Bytes in Host RX Endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint number
0x01C6 451A HOST_TXTYPE
for the host TX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
0x01C6 451B HOST_TXINTERVAL
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
0x01C6 451C HOST_RXTYPE
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
0x01C6 451D HOST_RXINTERVAL
timeout on Bulk transactions for host RX endpoint.
Control and Status Register for Endpoint 2 - EOCSR2
0x01C6 4520 TXMAXP Maximum Packet Size for Peripheral/Host TX Endpoint
PERI_TXCSR Control Status Register for Peripheral TX Endpoint
0x01C6 4522
HOST_TXCSR Control Status Register for Host TX Endpoint
0x01C6 4524 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint
PERI_RXCSR Control Status Register for Peripheral RX Endpoint
0x01C6 4526
HOST_RXCSR Control Status Register for Host RX Endpoint
0x01C6 4528 RXCOUNT Number of Bytes in Host RX Endpoint FIFO
Sets the operating speed, transaction protocol and peripheral endpoint number
0x01C6 452A HOST_TXTYPE
for the host TX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
0x01C6 452B HOST_TXINTERVAL
timeout on Bulk transactions for host TX endpoint.
Sets the operating speed, transaction protocol and peripheral endpoint number
0x01C6 452C HOST_RXTYPE
for the host RX endpoint.
Sets the polling interval for Interrupt/ISOC transactions or the NAK response
0x01C6 452D HOST_RXINTERVAL
timeout on Bulk transactions for host RX endpoint.
Control and Status Register for Endpoint 3 - EOCSR3
0x01C6 4530 TXMAXP Maximum Packet Size for Peripheral/Host TX Endpoint
PERI_TXCSR Control Status Register for Peripheral TX Endpoint
0x01C6 4532
HOST_TXCSR Control Status Register for Host TX Endpoint
0x01C6 4534 RXMAXP Maximum Packet Size for Peripheral/Host RX Endpoint
PERI_RXCSR Control Status Register for Peripheral RX Endpoint
0x01C6 4536
HOST_RXCSR Control Status Register for Host RX Endpoint
0x01C6 4538 RXCOUNT Number of Bytes in Host RX Endpoint FIFO
276 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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