Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-86. USB2.0 Registers (continued)
HEX ADDRESS
ACRONYM REGISTER NAME
RANGE
0x01C6 41B8 RCPPIDMASTATEW6 RX CPPI DMA State Word 6
0x01C6 41BC RCPPICOMPPTR RX CPPI Completion Pointer
TX/RX CCPI Channel 3 State Block
0x01C6 41C0 TCPPIDMASTATEW0 TX CPPI DMA State Word 0
0x01C6 41C4 TCPPIDMASTATEW1 TX CPPI DMA State Word 1
0x01C6 41C8 TCPPIDMASTATEW2 TX CPPI DMA State Word 2
0x01C6 41CC TCPPIDMASTATEW3 TX CPPI DMA State Word 3
0x01C6 41D0 TCPPIDMASTATEW4 TX CPPI DMA State Word 4
0x01C6 41D4 TCPPIDMASTATEW5 TX CPPI DMA State Word 5
0x01C6 41D8 – Rserved
0x01C6 41DC TCPPICOMPPTR TX CPPI Completion Pointer
0x01C6 41E0 RCPPIDMASTATEW0 RX CPPI DMA State Word 0
0x01C6 41E4 RCPPIDMASTATEW1 RX CPPI DMA State Word 1
0x01C6 41E8 RCPPIDMASTATEW2 RX CPPI DMA State Word 2
0x01C6 41EC RCPPIDMASTATEW3 RX CPPI DMA State Word 3
0x01C6 41F0 RCPPIDMASTATEW4 RX CPPI DMA State Word 4
0x01C6 41F4 RCPPIDMASTATEW5 RX CPPI DMA State Word 5
0x01C6 41F8 RCPPIDMASTATEW6 RX CPPI DMA State Word 6
0x01C6 41FC RCPPICOMPPTR RX CPPI Completion Pointer
0x01C6 4200 - Reserved
–
0x01C6 43FF
Core Registers
0x01C6 4400 FADDR Function Address Register
0x01C6 4401 POWER Power Management Register
0x01C6 4402 INTRTX Interrupt Register for Endpoint 0 plus TX Endpoints 1 to 4
0x01C6 4404 INTRRX Interrupt Register for RX Endpoints 1 to 4
0x01C6 4406 INTRTXE Interrupt Enable Register for INTRTX
0x01C6 4408 INTRRXE Interrupt Enable Register for INTRRX
0x01C6 440A INTRUSB Interrupt Register for Common USB Interrupts
0x01C6 440B INTRUSBE Interrupt Enable Register for INTRUSB
0x01C6 440C FRAME Frame Number Register
0x01C6 440E INDEX Index register for selecting the endpoint status and control registers
0x01C6 440F TESTMODE Register to enable the USB 2.0 test modes
Maximum packet size for peripheral/host TX endpoint (Index register set to select
0x01C6 4410 TXMAXP
Endpoints 1 - 4 only)
Control Status register for Endpoint 0 in Peripheral mode. (Index register set to
PERI_CSR0
select Endpoint 0)
Control Status register for Endpoint 0 in Host mode. (Index register set to select
HOST_CSR0
Endpoint 0)
0x01C6 4412
Control Status register for peripheral TX endpoint. (Index register set to select
PERI_TXCSR
Endpoints 1 - 4)
Control Status register for host TX endpoint. (Index register set to select
HOST_TXCSR
Endpoints 1 - 4)
Maximum packet size for peripheral/host RX endpoint (Index register set to select
0x01C6 4414 RXMAXP
Endpoints 1 - 4 only)
Control Status register for peripheral RX endpoint. (Index register set to select
PERI_RXCSR
Endpoints 1 - 4)
0x01C6 4416
Control Status register for host RX endpoint. (Index register set to select
HOST_RXCSR
Endpoints 1 - 4)
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 273
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T