Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
7.18 Host-Port Interface (HPI) Peripheral
The HPI is a parallel port through which a host processor can directly access the CPU memory space.
The host device functions as a master to the interface, which increases ease of access. The host and
CPU can exchange information via internal or external memory. The host also has direct access to
memory-mapped peripherals. Connectivity to the CPU memory space is provided through the EDMA3
controller.
7.18.1 HPI Device-Specific Information
The DM6467T device includes a user-configurable 32- or 16-bit Host-port interface (HPI32/HPI16).
• Multiplexed (address/data) operation
• Configurable single full-word cycle and dual half-word cycle access modes
• Bursting available utilizing 8-word read and write FIFOs
• HPIA register supports auto-incrementing
• HPID register/FIFOs providing data-path between external host interface and system bus
• Multiple strobes and control signals to allow flexible host connection
• Configurable asynchronous HRDY output to allow HPI to insert wait states to the Host [System Module
Register HPICTL.HRDYMODE]
• Software control of data prefetching to the HPID/FIFOs
• DMSoC-to-Host interrupt output signal controlled by HPIC accesses
• Host-to-DMSoC interrupt controlled by HPIC accesses
NOTE: The DM6467T HPI does not support the HAS feature. For proper HPI operation if the HAS pin
(D4) is routed out, the HAS pin must be pulled up via an external resistor.
The DM6467T HPICTL register (0x01C4 0030) is part of the System Module Registers. The HPICTL
register controls write access to the HPI peripheral control and address registers as well as determines
the host time-out value. The HPICTL System Module Register also determines the operation of the HRDY
output which allows the HPI to insert wait states to the Host. For more detailed information on the HPICTL
System Module Register, see Section 4.6.2, Peripheral Selection After Device Reset.
For more detailed information on the HPI peripheral, see the TMS320DM646x DMSoC Host Port Interface
(HPI) User's Guide (literature number SPRUES1).
7.18.2 HPI Bus Master
The HPI peripheral includes a bus master interface that allows external device initiated transfers to access
the DM6467T system bus. Table 7-81 shows the memory map for the HPI master interface.
Table 7-81. HPI Master Memory Map
SIZE
START ADDRESS END ADDRESS HPI ACCESS
(BYTES)
0x0000 0000 0x01BF FFFF 28M Reserved
0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals
0x1000 0000 0x1000 FFFF 64K Reserved
0x1001 0000 0x1001 3FFF 16K ARM RAM 0 (Data)
0x1001 4000 0x1001 7FFF 16K ARM RAM 1 (Data)
0x1001 8000 0x1001 FFFF 32K ARM ROM (Data)
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