Datasheet

MRCLK (Input)
1
2
MRXD7−MRXD4(GMII only),
MRXD3−MRXD0,
MRXDV, MRXER (Inputs)
GMTCLK
(Output)
2 3
1
4
4
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-74. Switching Characteristics Over Recommended Operating Conditions for GMTCLK - GMII
Operation (see Figure 7-52)
-1G
NO. PARAMETER 1000 Mbps UNIT
MIN MAX
1 t
c(GMTCLK)
Cycle time, GMTCLK 8 ns
2 t
w(GMTCLKH)
Pulse duration, GMTCLK high 2.8 ns
3 t
w(GMTCLKL)
Pulse duration, GMTCLK low 2.8 ns
4 t
t(GMTCLK)
Transition time, GMTCLK 1 ns
Figure 7-52. GMTCLK Timing (EMAC – Transmit) [GMII Operation]
Table 7-75. Timing Requirements for EMAC MII and GMII Receive 10/100/1000 Mbit/s
(1)
(see Figure 7-53)
-1G
NO. 1000 Mbps 100/10 Mbps UNIT
MIN MAX MIN MAX
Setup time, receive selected signals valid before
1 t
su(MRXD-MRCLKH)
2 8 ns
MRCLK high
Hold time, receive selected signals valid after
2 t
h(MRCLKH-MRXD)
0 8 ns
MRCLK high
(1) For MII, Receive selected signals include: MRXD[3:0], MRXDV, and MRXER.
For GMII, Receive selected signals include: MRXD[7:0], MRXDV, and MRXER.
Figure 7-53. EMAC Receive Interface Timing [MII and GMII Operation]
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 257
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T