Datasheet

MTCLK
(Input)
2 3
1
4
4
MRCLK
(Input)
2 3
1
4
4
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.16.4 EMAC Electrical Data/Timing
Table 7-71. Timing Requirements for MRCLK - MII and GMII Operation (see Figure 7-49)
-1G
1000 Mbps
NO. 100 Mbps 10 Mbps UNIT
(GMII Only)
MIN MAX MIN MAX MIN MAX
1 t
c(MRCLK)
Cycle time, MRCLK 8 40 400 ns
2 t
w(MRCLKH)
Pulse duration, MRCLK high 2.8 14 140 ns
3 t
w(MRCLKL)
Pulse duration, MRCLK low 2.8 14 140 ns
4 t
t(MRCLK)
Transition time, MRCLK 1 3 3 ns
Figure 7-49. MRCLK Timing (EMAC – Receive) [MII and GMII Operation]
Table 7-72. Timing Requirements for MTCLK - MII and GMII Operation (see Figure 7-50)
-1G
NO. 100 Mbps 10 Mbps UNIT
MIN MAX MIN MAX
1 t
c(MTCLK)
Cycle time, MTCLK 40 400 ns
2 t
w(MTCLKH)
Pulse duration, MTCLK high 14 140 ns
3 t
w(MTCLKL)
Pulse duration, MTCLK low 14 140 ns
4 t
t(MTCLK)
Transition time, MTCLK 3 3 ns
Figure 7-50. MTCLK Timing (EMAC – Transmit) [MII and GMII Operation]
Table 7-73. Timing Requirements for RFTCLK - GMII Operation (see Figure 7-51)
-1G
NO. 1000 Mbps UNIT
MIN MAX
1 t
c(RFTCLK)
Cycle time, RFTCLK 8 ns
2 t
w(RFTCLKH)
Pulse duration, RFTCLK high 2.8 ns
3 t
w(RFTCLKL)
Pulse duration, RFTCLK low 2.8 ns
4 t
t(RFTCLK)
Transition time, RFTCLK 1 ns
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 255
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