Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 7-68. EMAC Statistics Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C8 0244 TXDEFERRED Deferred transmit frames register
0x01C8 0248 TXCOLLISION Transmit collision frames register
0x01C8 024C TXSINGLECOLL Transmit single collision frames register
0x01C8 0250 TXMULTICOLL Transmit multiple collision frames register
0x01C8 0254 TXEXCESSIVECOLL Transmit excessive collision frames register
0x01C8 0258 TXLATECOLL Transmit late collision frames register
0x01C8 025C TXUNDERRUN Transmit underrun error register
0x01C8 0260 TXCARRIERSENSE Transmit carrier sense errors register
0x01C8 0264 TXOCTETS Transmit octet frames register
0x01C8 0268 FRAME64 Transmit and receive 64 octet frames register
0x01C8 026C FRAME65T127 Transmit and receive 65 to 127 octet frames register
0x01C8 0270 FRAME128T255 Transmit and receive 128 to 255 octet frames register
0x01C8 0274 FRAME256T511 Transmit and receive 256 to 511 octet frames register
0x01C8 0278 FRAME512T1023 Transmit and receive 512 to 1023 octet frames register
0x01C8 027C FRAME1024TUP Transmit and receive 1024 to 1518 octet frames register
0x01C8 0280 NETOCTETS Network octet frames register
0x01C8 0284 RXSOFOVERRUNS Receive FIFO or DMA start of frame overruns register
0x01C8 0288 RXMOFOVERRUNS Receive FIFO or DMA middle of frame overruns register
0x01C8 028C RXDMAOVERRUNS Receive DMA start of frame and middle of frame overruns register
0x01C8 0290 - 0x01C8 02FF – Reserved
Table 7-69. EMAC Control Module Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C8 1000 CMIDVER Identification and version register
0x01C8 1004 CMSOFTRESET Software reset register
0x01C8 1008 CMEMCONTROL Emulation control register
0x01C8 100C CMINTCTRL Interrupt control register
0x01C8 1010 CMRXTHRESHINTEN Receive threshold interrupt enable register
0x01C8 1014 CMRXINTEN Receive interrupt enable register
0x01C8 1018 CMTXINTEN Transmit interrupt enable register
0x01C8 101C CMMISCINTEN Miscellaneous interrupt enable register
0x01C8 1020 - 0x01C8 103F – Reserved
0x01C8 1040 CMRXTHRESHINTSTAT Receive threshold interrupt status register
0x01C8 1044 CMRXINTSTAT Receive interrupt status register
0x01C8 1048 CMTXINTSTAT Transmit interrupt status register
0x01C8 104C CMMISCINTSTAT Miscellaneous interrupt status register
0x01C8 1050 - 0x01C8 106F – Reserved
0x01C8 1070 CMRXINTMAX Receive interrupts per millisecond register
0x01C8 1074 CMTXINTMAX Transmit interrupts per millisecond register
0x01C8 1078 - 0x01C8 10FF – Reserved
0x01C8 1100 - 0x01C8 1FFF – Reserved
Table 7-70. EMAC Descriptor Memory
HEX ADDRESS RANGE ACRONYM DESCRIPTION
0x01C8 2000 - 0x01C8 3FFF – EMAC Control Module Descriptor Memory
254 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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