Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-67. Ethernet MAC (EMAC) Control Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
Transmit channel 4 completion pointer (interrupt acknowledge)
0x01C8 0650 TX4CP
register
Transmit channel 5 completion pointer (interrupt acknowledge)
0x01C8 0654 TX5CP
register
Transmit channel 6 completion pointer (interrupt acknowledge)
0x01C8 0658 TX6CP
register
Transmit channel 7 completion pointer (interrupt acknowledge)
0x01C8 065C TX7CP
register
Receive channel 0 completion pointer (interrupt acknowledge)
0x01C8 0660 RX0CP
register
Receive channel 1 completion pointer (interrupt acknowledge)
0x01C8 0664 RX1CP
register
Receive channel 2 completion pointer (interrupt acknowledge)
0x01C8 0668 RX2CP
register
Receive channel 3 completion pointer (interrupt acknowledge)
0x01C8 066C RX3CP
register
Receive channel 4 completion pointer (interrupt acknowledge)
0x01C8 0670 RX4CP
register
Receive channel 5 completion pointer (interrupt acknowledge)
0x01C8 0674 RX5CP
register
Receive channel 6 completion pointer (interrupt acknowledge)
0x01C8 0678 RX6CP
register
Receive channel 7 completion pointer (interrupt acknowledge)
0x01C8 067C RX7CP
register
0x01C8 0680 - 0x01C8 07FF – Reserved
Table 7-68. EMAC Statistics Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C8 0200 RXGOODFRAMES Good receive frames register
Broadcast receive frames register
0x01C8 0204 RXBCASTFRAMES
(Total number of good broadcast frames received)
Multicast receive frames register
0x01C8 0208 RXMCASTFRAMES
(Total number of good multicast frames received)
0x01C8 020C RXPAUSEFRAMES Pause receive frames register
Receive CRC errors register
0x01C8 0210 RXCRCERRORS
(Total number of frames received with CRC errors)
Receive alignment/code errors register
0x01C8 0214 RXALIGNCODEERRORS
(Total number of frames received with alignment/code errors)
Receive oversized frames register
0x01C8 0218 RXOVERSIZED
(Total number of oversized frames received)
Receive jabber frames register
0x01C8 021C RXJABBER
(Total number of jabber frames received)
Receive undersized frames register
0x01C8 0220 RXUNDERSIZED
(Total number of undersized frames received)
0x01C8 0224 RXFRAGMENTS Receive Frame Fragments Register
0x01C8 0228 RXFILTERED Filtered receive frames register
0x01C8 022C RXQOSFILTERED Received QOS filtered frames register
Receive octet frames register
0x01C8 0230 RXOCTETS
(Total number of received bytes in good frames)
Good Transmit Frames Register
0x01C8 0234 TXGOODFRAMES
(Total number of good frames transmitted)
0x01C8 0238 TXBCASTFRAMES Broadcast transmit frames register
0x01C8 023C TXMCASTFRAMES Multicast transmit frames register
0x01C8 0240 TXPAUSEFRAMES Pause transmit frames register
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 253
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