Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
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SPRS605C –JULY 2009–REVISED JUNE 2012
7.16.3 EMAC Peripheral Register Description(s)
Table 7-67. Ethernet MAC (EMAC) Control Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C8 0000 TXIDVER Transmit identification and version register
0x01C8 0004 TXCONTROL Transmit control register
0x01C8 0008 TXTEARDOWN Transmit teardown register
0x01C8 000C - 0x01C8 000F – Reserved
0x01C8 0010 RXIDVER Receive identification and version register
0x01C8 0014 RXCONTROL Receive control register
0x01C8 0018 RXTEARDOWN Receive teardown register
0x01C8 001C - 0x01C8 007F – Reserved
0x01C8 0080 TXINTSTATRAW Transmit interrupt status (unmasked) register
0x01C8 0084 TXINTSTATMASKED Transmit interrupt status (masked) register
0x01C8 0088 TXINTMASKSET Transmit interrupt mask set register
0x01C8 008C TXINTMASKCLEAR Transmit interrupt mask clear register
0x01C8 0090 MACINVECTOR MAC input vector register
0x01C8 0094 MACEOIVECTOR MAC end of interrupt vector register
0x01C8 0098 - 0x01C8 009F – Reserved
0x01C8 00A0 RXINTSTATRAW Receive interrupt status (unmasked) register
0x01C8 00A4 RXINTSTATMASKED Receive interrupt status (masked) register
0x01C8 00A8 RXINTMASKSET Receive interrupt mask set register
0x01C8 00AC RXINTMASKCLEAR Receive interrupt mask clear register
0x01C8 00B0 MACINTSTATRAW MAC interrupt status (unmasked) register
0x01C8 00B4 MACINTSTATMASKED MAC interrupt status (masked) register
0x01C8 00B8 MACINTMASKSET MAC interrupt mask set register
0x01C8 00BC MACINTMASKCLEAR MAC interrupt mask clear register
0x01C8 00C0 - 0x01C8 00FF – Reserved
0x01C8 0100 RXMBPENABLE Receive multicast/broadcast/promiscuous channel enable register
0x01C8 0104 RXUNICASTSET Receive unicast enable set register
0x01C8 0108 RXUNICASTCLEAR Receive unicast clear register
0x01C8 010C RXMAXLEN Receive maximum length register
0x01C8 0110 RXBUFFEROFFSET Receive buffer offset register
0x01C8 0114 RXFILTERLOWTHRESH Receive filter low priority frame threshold register
0x01C8 0118 - 0x01C8 011F – Reserved
0x01C8 0120 RX0FLOWTHRESH Receive channel 0 flow control threshold register
0x01C8 0124 RX1FLOWTHRESH Receive channel 1 flow control threshold register
0x01C8 0128 RX2FLOWTHRESH Receive channel 2 flow control threshold register
0x01C8 012C RX3FLOWTHRESH Receive channel 3 flow control threshold register
0x01C8 0130 RX4FLOWTHRESH Receive channel 4 flow control threshold register
0x01C8 0134 RX5FLOWTHRESH Receive channel 5 flow control threshold register
0x01C8 0138 RX6FLOWTHRESH Receive channel 6 flow control threshold register
0x01C8 013C RX7FLOWTHRESH Receive channel 7 flow control threshold register
0x01C8 0140 RX0FREEBUFFER Receive channel 0 free buffer count register
0x01C8 0144 RX1FREEBUFFER Receive channel 1 free buffer count register
0x01C8 0148 RX2FREEBUFFER Receive channel 2 free buffer count register
0x01C8 014C RX3FREEBUFFER Receive channel 3 free buffer count register
0x01C8 0150 RX4FREEBUFFER Receive channel 4 free buffer count register
0x01C8 0154 RX5FREEBUFFER Receive channel 5 free buffer count register
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 251
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