Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-64. PCI Hook Configuration Registers
DMSoC ACCESS
ACRONYM DMSoC ACCESS REGISTER NAME
HEX ADDRESS RANGE
01C1 A394 PCIVENDEVPRG PCI Vendor ID and Device ID Program Register
01C1 A398 – Reserved
01C1 A39C PCICLREVPRG PCI Class Code and Revision ID Program Register
01C1 A3A0 PCISUBIDPRG PCI Subsystem Vendor ID and Subsystem ID Program Register
01C1 A3A4 PCIMAXLGPRG PCI Max Latency and Min Grant Program Register
01C1 A3A8 – Reserved
01C1 A3AC PCICFGDONE PCI Configuration Done Register
01C1 A3B0 - 01C1 A3FB – Reserved
01C1 A3FC - 01C1 A3FF – Reserved
01C1 A400 - 01C1 A7FF – Reserved
Table 7-65. PCI External Memory Space
DMSoC HEX ADDRESS
ACRONYM DESCRIPTION
RANGE
3000 0000 - 307F FFFF – PCI Master Window 0
3080 0000 - 30FF FFFF – PCI Master Window 1
3100 0000 - 317F FFFF – PCI Master Window 2
3180 0000 - 31FF FFFF – PCI Master Window 3
3200 0000 - 327F FFFF – PCI Master Window 4
3280 0000 - 32FF FFFF – PCI Master Window 5
3300 0000 - 337F FFFF – PCI Master Window 6
3380 0000 - 33FF FFFF – PCI Master Window 7
3400 0000 - 347F FFFF – PCI Master Window 8
3480 0000 - 34FF FFFF – PCI Master Window 9
3500 0000 - 357F FFFF – PCI Master Window 10
3580 0000 - 35FF FFFF – PCI Master Window 11
3600 0000 - 367F FFFF – PCI Master Window 12
3680 0000 - 36FF FFFF – PCI Master Window 13
3700 0000 - 377F FFFF – PCI Master Window 14
3780 0000 - 37FF FFFF – PCI Master Window 15
3800 0000 - 387F FFFF – PCI Master Window 16
3880 0000 - 38FF FFFF – PCI Master Window 17
3900 0000 - 397F FFFF – PCI Master Window 18
3980 0000 - 39FF FFFF – PCI Master Window 19
3A00 0000 - 3A7F FFFF – PCI Master Window 20
3A80 0000 - 3AFF FFFF – PCI Master Window 21
3B00 0000 - 3B7F FFFF – PCI Master Window 22
3B80 0000 - 3BFF FFFF – PCI Master Window 23
3C00 0000 - 3C7F FFFF – PCI Master Window 24
3C80 0000 - 3CFF FFFF – PCI Master Window 25
3D00 0000 - 3D7F FFFF – PCI Master Window 26
3D80 0000 - 3DFF FFFF – PCI Master Window 27
3E00 0000 - 3E7F FFFF – PCI Master Window 28
3E80 0000 - 3EFF FFFF – PCI Master Window 29
3F00 0000 - 3F7F FFFF – PCI Master Window 30
3F80 0000 - 3FFF FFFF – PCI Master Window 31
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