Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 7-62. PCI Back End Configuration Registers (continued)
DMSoC ACCESS
ACRONYM DMSoC ACCESS REGISTER NAME
HEX ADDRESS RANGE
01C1 A304 PCIMCFGADR PCI Master Configuration/IO Access Address Register
01C1 A308 PCIMCFGCMD PCI Master Configuration/IO Access Command Register
01C1 A30C - 01C1 A30F - Reserved
01C1 A310 PCIMSTCFG PCI Master Configuration Register
Table 7-63. DMSoC-to-PCI Address Translation Registers
DMSoC ACCESS
ACRONYM DMSoC ACCESS REGISTER NAME
HEX ADDRESS RANGE
01C1 A314 PCIADDSUB0 PCI Address Substitute 0 Register
01C1 A318 PCIADDSUB1 PCI Address Substitute 1 Register
01C1 A31C PCIADDSUB2 PCI Address Substitute 2 Register
01C1 A320 PCIADDSUB3 PCI Address Substitute 3 Register
01C1 A324 PCIADDSUB4 PCI Address Substitute 4 Register
01C1 A328 PCIADDSUB5 PCI Address Substitute 5 Register
01C1 A32C PCIADDSUB6 PCI Address Substitute 6 Register
01C1 A330 PCIADDSUB7 PCI Address Substitute 7 Register
01C1 A334 PCIADDSUB8 PCI Address Substitute 8 Register
01C1 A338 PCIADDSUB9 PCI Address Substitute 9 Register
01C1 A33C PCIADDSUB10 PCI Address Substitute 10 Register
01C1 A340 PCIADDSUB11 PCI Address Substitute 11 Register
01C1 A344 PCIADDSUB12 PCI Address Substitute 12 Register
01C1 A348 PCIADDSUB13 PCI Address Substitute 13 Register
01C1 A34C PCIADDSUB14 PCI Address Substitute 14 Register
01C1 A350 PCIADDSUB15 PCI Address Substitute 15 Register
01C1 A354 PCIADDSUB16 PCI Address Substitute 16 Register
01C1 A358 PCIADDSUB17 PCI Address Substitute 17 Register
01C1 A35C PCIADDSUB18 PCI Address Substitute 18 Register
01C1 A360 PCIADDSUB19 PCI Address Substitute 19 Register
01C1 A364 PCIADDSUB20 PCI Address Substitute 20 Register
01C1 A368 PCIADDSUB21 PCI Address Substitute 21 Register
01C1 A36C PCIADDSUB22 PCI Address Substitute 22 Register
01C1 A370 PCIADDSUB23 PCI Address Substitute 23 Register
01C1 A374 PCIADDSUB24 PCI Address Substitute 24 Register
01C1 A378 PCIADDSUB25 PCI Address Substitute 25 Register
01C1 A37C PCIADDSUB26 PCI Address Substitute 26 Register
01C1 A380 PCIADDSUB27 PCI Address Substitute 27 Register
01C1 A384 PCIADDSUB28 PCI Address Substitute 28 Register
01C1 A388 PCIADDSUB29 PCI Address Substitute 29 Register
01C1 A38C PCIADDSUB30 PCI Address Substitute 30 Register
01C1 A390 PCIADDSUB31 PCI Address Substitute 31 Register
246 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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