Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
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SPRS605C –JULY 2009–REVISED JUNE 2012
7.15.3 PCI Peripheral Register Description(s)
Table 7-62. PCI Back End Configuration Registers
DMSoC ACCESS
ACRONYM DMSoC ACCESS REGISTER NAME
HEX ADDRESS RANGE
01C1 A000 - 01C1 A00F - Reserved
01C1 A010 PCISTATSET PCI Status Set Register
01C1 A014 PCISTATCLR PCI Status Clear Register
01C1 A018 - 01C1 A01F - Reserved
01C1 A020 PCIHINTSET PCI Host Interrupt Enable Set Register
01C1 A024 PCIHINTCLR PCI Host Interrupt Enable Clear Register
01C1 A028 - 01C1 A02F - Reserved
01C1 A030 PCIBINTSET PCI Back End Application Interrupt Enable Set Register
01C1 A034 PCIBINTCLR PCI Back End Application Interrupt Enable Clear Register
01C1 A038 - Reserved
01C1 A03C - 01C1 A0FF - Reserved
01C1 A100 PCIVENDEVMIR PCI Vendor ID/Device ID Mirror Register
01C1 A104 PCICSRMIR PCI Command/Status Mirror Register
01C1 A108 PCICLREVMIR PCI Class Code/Revision ID Mirror Register
01C1 A10C PCICLINEMIR PCI BIST/Header Type/Latency Timer/Cacheline Size Mirror Register
01C1 A110 PCIBAR0MSK PCI Base Address Mask Register 0
01C1 A114 PCIBAR1MSK PCI Base Address Mask Register 1
01C1 A118 PCIBAR2MSK PCI Base Address Mask Register 2
01C1 A11C PCIBAR3MSK PCI Base Address Mask Register 3
01C1 A120 PCIBAR4MSK PCI Base Address Mask Register 4
01C1 A124 PCIBAR5MSK PCI Base Address Mask Register 5
01C1 A128 - 01C1 A12B - Reserved
01C1 A12C PCISUBIDMIR PCI Subsystem Vendor ID/Subsystem ID Mirror Register
01C1 A130 - Reserved
01C1 A134 PCICPBPTRMIR PCI Capabilities Pointer Mirror Register
01C1 A138 - 01C1 A13B - Reserved
01C1 A13C PCILGINTMIR PCI Max Latency/Min Grant/Interrupt Pin/Interrupt Line Mirror Register
01C1 A140 - 01C1 A17F - Reserved
01C1 A180 PCISLVCNTL PCI Slave Control Register
01C1 A184 - 01C1 A1BF - Reserved
01C1 A1C0 PCIBAR0TRL PCI Slave Base Address 0 Translation Register
01C1 A1C4 PCIBAR1TRL PCI Slave Base Address 1 Translation Register
01C1 A1C8 PCIBAR2TRL PCI Slave Base Address 2 Translation Register
01C1 A1CC PCIBAR3TRL PCI Slave Base Address 3 Translation Register
01C1 A1D0 PCIBAR4TRL PCI Slave Base Address 4 Translation Register
01C1 A1D4 PCIBAR5TRL PCI Slave Base Address 5 Translation Register
01C1 A1D8 - 01C1 A1DF - Reserved
01C1 A1E0 PCIBAR0MIR PCI Base Address Register 0 Mirror Register
01C1 A1E4 PCIBAR1MIR PCI Base Address Register 1 Mirror Register
01C1 A1E8 PCIBAR2MIR PCI Base Address Register 2 Mirror Register
01C1 A1EC PCIBAR3MIR PCI Base Address Register 3 Mirror Register
01C1 A1F0 PCIBAR4MIR PCI Base Address Register 4 Mirror Register
01C1 A1F4 PCIBAR5MIR PCI Base Address Register 5 Mirror Register
01C1 A1F8 - 01C1 A2FF - Reserved
01C1 A300 PCIMCFGDAT PCI Master Configuration/IO Access Data Register
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