Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
7.14.2 VDCE Register Description(s)
Table 7-59 shows the VDCE registers.
Table 7-59. VDCE Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 2800 PID VDCE peripheral identification register
0x01C1 2804 CTRL VDCE control register
0x01C1 2808 INTEN Interrupt enable register
0x01C1 280C INTEN_SET Interrupt enable set register
0x01C1 2810 INTEN_CLR Interrupt enable clear register
0x01C1 2814 INTSTAT Interrupt status register
0x01C1 2818 INTSTAT_CLR Interrupt status clear register
0x01C1 281C EMU_CTRL Emulation control register
0x01C1 2820 SRD_FRMT Source/Result data store format register
0x01C1 2824 REQ_SIZE Request unit size register
0x01C1 2828 PROC_SIZE Processing unit size register
0x01C1 282C - 0x01C1 283F – Reserved
0x01C1 2840 TY_SRCADDR Luma top field source start address register
0x01C1 2844 TY_SRCSPSIZE Luma top field source sub-picture size register
0x01C1 2848 TY_SRCOFFSET Luma top field line source address offset size register
0x01C1 284C BY_SRCADDR Luma bottom field source start address register
0x01C1 2850 BY_SRCSPSIZE Luma bottom field source sub-picture size register
0x01C1 2854 BY_SRCOFFSET Luma bottom field line source address offset size register
0x01C1 2858 TC_SRCADDR Chroma top field source start address register
0x01C1 285C TC_SRCSPSIZE Chroma top field source sub-picture size register
0x01C1 2860 TC_SRCOFFSET Chroma top field line source address offset size register
0x01C1 2864 BC_SRCADDR Chroma bottom field source start address register
0x01C1 2868 BC_SRCSPSIZE Chroma bottom field source sub-picture size register
0x01C1 286C BC_SRCOFFSET Chroma bottom field line source address offset size register
0x01C1 2870 TBMP_SRCADDR Bitmap top field source start address register
0x01C1 2874 TBMP_SRCOFFSET Bitmap top field line source address offset register
0x01C1 2878 BBMP_SRCADDR Bitmap bottom field source start address register
0x01C1 287C BBMP_SRCOFFSET Bitmap bottom field line source address offset register
0x01C1 2880 TY_RESADDR Luma top field result start address register
0x01C1 2884 TY_RESSPSIZE Luma top field result sub-picture size register
0x01C1 2888 TY_RESOFFSET Luma top field line result address offset size register
0x01C1 288C BY_RESADDR Luma bottom field result start address register
0x01C1 2890 BY_RESSPSIZE Luma bottom field result sub-picture size register
0x01C1 2894 BY_RESOFFSET Luma bottom field line result address offset size register
0x01C1 2898 TC_RESADDR Chroma top field result start address register
0x01C1 289C TC_RESSPSIZE Chroma top field result sub-picture size register
0x01C1 28A0 TC_RESOFFSET Chroma top field result line address offset size register
0x01C1 28A4 BC_RESADDR Chroma bottom field result start address register
0x01C1 28A8 BC_RESSPSIZE Chroma bottom field result sub-picture size register
0x01C1 28AC BC_RESOFFSET Chroma bottom field line result address offset size register
0x01C1 28B0 - 0x01C1 28BF – Reserved
0x01C1 28C0 IMG_Y_SRCSTRTPOS Luminance source image start position register
0x01C1 28C4 IMG_Y_SRCSIZE Luminance source image size register
0x01C1 28C8 IMG_C_SRCSTRTPOS Chrominance source image start position register
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 241
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