Datasheet

Table Of Contents
TMS320DM6467T
SPRS605C JULY 2009REVISED JUNE 2012
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Table 7-50. TSIF0 Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 314C WRB4_SUB Write ring buffer channel 4 subtraction register
0x01C1 3150 WRB4_WRPTR Write ring buffer channel 4 write pointer register
0x01C1 3154 - 0x01C1 315F Reserved
0x01C1 3160 WRB5_STRT_ADDR Write ring buffer channel 5 start address register
0x01C1 3164 WRB5_END_ADDR Write ring buffer channel 5 end address register
0x01C1 3168 WRB5_RDPTR Write ring buffer channel 5 read pointer register
0x01C1 316C WRB5_SUB Write ring buffer channel 5 subtraction register
0x01C1 3170 WRB5_WRPTR Write ring buffer channel 5 write pointer register
0x01C1 3174 - 0x01C1 317F Reserved
0x01C1 3180 WRB6_STRT_ADDR Write ring buffer channel 6 start address register
0x01C1 3184 WRB6_END_ADDR Write ring buffer channel 6 end address register
0x01C1 3188 WRB6_RDPTR Write ring buffer channel 6 read pointer register
0x01C1 318C WRB6_SUB Write ring buffer channel 6 subtraction register
0x01C1 3190 WRB6_WRPTR Write ring buffer channel 6 write pointer register
0x01C1 3194 - 0x01C1 319F Reserved
0x01C1 31A0 WRB7_STRT_ADDR Write ring buffer channel 7 start address register
0x01C1 31A4 WRB7_END_ADDR Write ring buffer channel 7 end address register
0x01C1 31A8 WRB7_RDPTR Write ring buffer channel 7 read pointer register
0x01C1 31AC WRB7_SUB Write ring buffer channel 7 subtraction register
0x01C1 31B0 WRB7_WRPTR Write ring buffer channel 7 write pointer register
0x01C1 31B4 - 0x01C1 31BF Reserved
0x01C1 31C0 RRB_CTRL Read ring buffer channel control register
0x01C1 31C4 RRB_STRT_ADDR Read ring buffer channel start address register
0x01C1 31C8 RRB_END_ADDR Read ring buffer channel end address register
0x01C1 31CC RRB_WRPTR Read ring buffer channel write pointer register
0x01C1 31D0 RRB_SUB Read ring buffer channel subtraction register
0x01C1 31D4 RRB_RDPTR Read ring buffer channel read pointer register
0x01C1 31D8 PKT_CNT Packet counter value register
0x01C1 31DC - 0x01C1 31FF Reserved
Table 7-51. TSIF1 Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 3400 PID TSIF1 peripheral identification (PID) register
0x01C1 3404 CTRL0 Control register 0 register
0x01C1 3408 CTRL1 Control register 1 register
0x01C1 340C INTEN Interrupt enable register
0x01C1 3410 INTEN_SET Interrupt enable set register
0x01C1 3414 INTEN_CLR Interrupt enable clear register
0x01C1 3418 INTSTAT Interrupt status register
0x01C1 341C INTSTAT_CLR Interrupt status clear register
0x01C1 3420 EMU_CTRL Emulation control register
0x01C1 3424 ASYNC_TX_WAIT Asynchronous transmit wait time register
0x01C1 3428 PAT_SEN_CFG Program association table (PAT) sense configuration register
0x01C1 342C PAT_STR_ADDR PAT store address register
0x01C1 3430 PMT_SEN_CFG Program map table (PMT) sense configuration register
0x01C1 3434 PMT_STR_ADDR PMT store address register
0x01C1 3438 BSP_IN Boundary sensing packet (BSP) in register
232 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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