Datasheet

Table Of Contents
1000
0101
0000
0100
TSIFCTL.TSSO_CLK
TS1_CLKIN
VP_CLKIN0
TSIF1
OutputClockSource
TS1_CLKIN
VP_CLKIN0
CRG1_VCXI
CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
0011
SYSCLKBP
PLL
Controller1
VSCLKDIS.TSIFTX1
PINMUX0.CRGMUX
0001
STC_CLKIN
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
GP[4]/STC_CLKIN
DEV_MXI/DEV_CLKIN
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
0110
VP_CLKIN2
VP_CLKIN2
0010
SYSCLK6
(A) 0111, 1001–1xx1 = Reserved.
001
TSIFCTL.TSIF0_CNTCLK
TSIF0
CounterClock
STC_CLKIN
010
AUXCLK
PLL
Controller1
VSCLKDIS.TSIFCNT0
GP[4]/STC_CLKIN
DEV_MXI/DEV_CLKIN
000
CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
PINMUX0.CRGMUX
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
100
011
VP_CLKIN0
VP_CLKIN0
CRG1_VCXI
101
VP_CLKIN1
VP_CLKIN1
(A)110,111=Reserved.
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
TMS320DM6467T
www.ti.com
SPRS605C JULY 2009REVISED JUNE 2012
Figure 7-42. TSIF0 Counter Clock Selection
TSIF1 outputs data synchronous to TS1_CLKO. The source clock for the TS1_CLKO output is selectable
from among a number of external clock inputs or on-chip clock sources (see Figure 7-43).
Figure 7-43. TSIF1 Output Clock Source Selection
The TSIF1 system time counter may be clocked from a number of external clock inputs or on-chip clock
sources (see Figure 7-44).
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