Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-45. Video Port Interface (VPIF) Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 20B0 CH1_VSIZE_CFG0 Channel 1 vertical data size configuration (0)
0x01C1 20B4 CH1_VSIZE_CFG1 Channel 1 vertical data size configuration (1)
0x01C1 20B8 CH1_VSIZE_CFG2 Channel 1 vertical data size configuration (2)
0x01C1 20BC CH1_VSIZE Channel 1 vertical image size
DISPLAY CHANNEL 2 REGISTERS
0x01C1 20C0 CH2_TY_STRTADR Channel 2 Top Field luma buffer start address
0x01C1 20C4 CH2_BY_STRTADR Channel 2 Bottom Field luma buffer start address
0x01C1 20C8 CH2_TC_STRTADR Channel 2 Top Field chroma buffer start address
0x01C1 20CC CH2_BC_STRTADR Channel 2 Bottom Field chroma buffer start address
0x01C1 20D0 CH2_THA_STRTADR Channel 2 Top Field horizontal ancillary data buffer start address
0x01C1 20D4 CH2_BHA_STRTADR Channel 2 Bottom Field horizontal ancillary data buffer start address
0x01C1 20D8 CH2_TVA_STRTADR Channel 2 Top Field vertical ancillary data buffer start address
0x01C1 20DC CH2_BVA_STRTADR Channel 2 Bottom Field vertical ancillary data buffer start address
0x01C1 20E0 CH2_SUBPIC_CFG Channel 2 sub-picture configuration
0x01C1 20E4 CH2_IMG_ADD_OFST Channel 2 image data address offset
0x01C1 20E8 CH2_HA_ADD_OFST Channel 2 horizontal ancillary data address offset
0x01C1 20EC CH2_HSIZE_CFG Channel 2 horizontal data size configuration
0x01C1 20F0 CH2_VSIZE_CFG0 Channel 2 vertical data size configuration (0)
0x01C1 20F4 CH2_VSIZE_CFG1 Channel 2 vertical data size configuration (1)
0x01C1 20F8 CH2_VSIZE_CFG2 Channel 2 vertical data size configuration (2)
0x01C1 20FC CH2_VSIZE Channel 2 vertical image size
0x01C1 2100 CH2_THA_STRTPOS Channel 2 Top Field horizontal ancillary data insertion start position
0x01C1 2104 CH2_THA_SIZE Channel 2 Top Field horizontal ancillary data size
0x01C1 2108 CH2_BHA_STRTPOS Channel 2 Bottom Field horizontal ancillary data insertion start position
0x01C1 210C CH2_BHA_SIZE Channel 2 Bottom Field horizontal ancillary data size
0x01C1 2110 CH2_TVA_STRTPOS Channel 2 Top Field vertical ancillary data insertion start position
0x01C1 2114 CH2_TVA_SIZE Channel 2 Top Field vertical ancillary data size
0x01C1 2118 CH2_BVA_STRTPOS Channel 2 Bottom Field vertical ancillary data insertion start position
0x01C1 211C CH2_BVA_SIZE Channel 2 Bottom Field vertical ancillary data size
0x01C1 2120 - 0x01C1 213F - Reserved
DISPLAY CHANNEL 3 REGISTERS
0x01C1 2140 CH3_TY_STRTADR Channel 3 Field 0 luma buffer start address
0x01C1 2144 CH3_BY_STRTADR Channel 3 Field 1 luma buffer start address
0x01C1 2148 CH3_TC_STRTADR Channel 3 Field 0 chroma buffer start address
0x01C1 214C CH3_BC_STRTADR Channel 3 Field 1 chroma buffer start address
0x01C1 2150 CH3_THA_STRTADR Channel 3 Field 0 horizontal ancillary data buffer start address
0x01C1 2154 CH3_BHA_STRTADR Channel 3 Field 1 horizontal ancillary data buffer start address
0x01C1 2158 CH3_TVA_STRTADR Channel 3 Field 0 vertical ancillary data buffer start address
0x01C1 215C CH3_BVA_STRTADR Channel 3 Field 1 vertical ancillary data buffer start address
0x01C1 2160 CH3_SUBPIC_CFG Channel 3 sub-picture configuration
0x01C1 2164 CH3_IMG_ADD_OFST Channel 3 image data address offset
0x01C1 2168 CH3_HA_ADD_OFST Channel 3 horizontal ancillary data address offset
0x01C1 216C CH3_HSIZE_CFG Channel 3 horizontal data size configuration
0x01C1 2170 CH3_VSIZE_CFG0 Channel 3 vertical data size configuration (0)
0x01C1 2174 CH3_VSIZE_CFG1 Channel 3 vertical data size configuration (1)
0x01C1 2178 CH3_VSIZE_CFG2 Channel 3 vertical data size configuration (2)
0x01C1 217C CH3_VSIZE Channel 3 vertical image size
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