Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
7.11.3 VPIF Register Descriptions
Table 7-45 shows the VPIF registers.
Table 7-45. Video Port Interface (VPIF) Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 2000 PID Peripheral identification register
0x01C1 2004 CH0_CTRL Channel 0 control register
0x01C1 2008 CH1_CTRL Channel 1 control register
0x01C1 200C CH2_CTRL Channel 2 control register
0x01C1 2010 CH3_CTRL Channel 3 control register
0x01C1 2014 - 0x01C1 201F - Reserved
0x01C1 2020 INTEN Interrupt enable
0x01C1 2024 INTENSET Interrupt enable set
0x01C1 2028 INTENCLR Interrupt enable clear
0x01C1 202C INTSTAT Interrupt status
0x01C1 2030 INTSTATCLR Interrupt status clear
0x01C1 2034 EMU_CTRL Emulation control
0x01C1 2038 DMA_SIZE DMA size control
0x01C1 203C - 0x01C1 203F - Reserved
CAPTURE CHANNEL 0 REGISTERS
0x01C1 2040 CH0_TY_STRTADR Channel 0 Top Field luma buffer start address
0x01C1 2044 CH0_BY_STRTADR Channel 0 Bottom Field luma buffer start address
0x01C1 2048 CH0_TC_STRTADR Channel 0 Top Field chroma buffer start address
0x01C1 204C CH0_BC_STRTADR Channel 0 Bottom Field chroma buffer start address
0x01C1 2050 CH0_THA_STRTADR Channel 0 Top Field horizontal ancillary data buffer start address
0x01C1 2054 CH0_BHA_STRTADR Channel 0 Bottom Field horizontal ancillary data buffer start address
0x01C1 2058 CH0_TVA_STRTADR Channel 0 Top Field vertical ancillary data buffer start address
0x01C1 205C CH0_BVA_STRTADR Channel 0 Bottom Field vertical ancillary data buffer start address
0x01C1 2060 CH0_SUBPIC_CFG Channel 0 sub-picture configuration
0x01C1 2064 CH0_IMG_ADD_OFST Channel 0 image data address offset
0x01C1 2068 CH0_HA_ADD_OFST Channel 0 horizontal ancillary data address offset
0x01C1 206C CH0_HSIZE_CFG Channel 0 horizontal data size configuration
0x01C1 2070 CH0_VSIZE_CFG0 Channel 0 vertical data size configuration (0)
0x01C1 2074 CH0_VSIZE_CFG1 Channel 0 vertical data size configuration (1)
0x01C1 2078 CH0_VSIZE_CFG2 Channel 0 vertical data size configuration (2)
0x01C1 207C CH0_VSIZE Channel 0 vertical image size
CAPTURE CHANNEL 1 REGISTERS
0x01C1 2080 CH1_TY_STRTADR Channel 1 Top Field luma buffer start address
0x01C1 2084 CH1_BY_STRTADR Channel 1 Bottom Field luma buffer start address
0x01C1 2088 CH1_TC_STRTADR Channel 1 Top Field chroma buffer start address
0x01C1 208C CH1_BC_STRTADR Channel 1 Bottom Field chroma buffer start address
0x01C1 2090 CH1_THA_STRTADR Channel 1 Top Field horizontal ancillary data buffer start address
0x01C1 2094 CH1_BHA_STRTADR Channel 1 Bottom Field horizontal ancillary data buffer start address
0x01C1 2098 CH1_TVA_STRTADR Channel 1 Top Field vertical ancillary data buffer start address
0x01C1 209C CH1_BVA_STRTADR Channel 1 Bottom Field vertical ancillary data buffer start address
0x01C1 20A0 CH1_SUBPIC_CFG Channel 1 sub-picture configuration
0x01C1 20A4 CH1_IMG_ADD_OFST Channel 1 image data address offset
0x01C1 20A8 CH1_HA_ADD_OFST Channel 1 horizontal ancillary data address offset
0x01C1 20AC CH1_HSIZE_CFG Channel 1 horizontal data size configuration
222 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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