Datasheet

Table Of Contents
000
110
100
101
VIDCLKCTL.VCH3CLK
VP_CLKIN2
GP[4]/STC_CLKIN
VPIF
Channel3
OutputClockSource
VP_CLKIN2
STC_CLKIN
VP_CLKIN0
CRG0_VCXI
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
11x
10x
011
AUXCLK
PLL
Controller1
VSCLKDIS.VID3
PINMUX0.CRGMUX
001
CRG1_VCXI
VP_CLKIN0
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
DEV_MXI/DEV_CLKIN
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
111
VP_CLKIN3/TS1_CLKO
VP_CLKIN3
010
SYSCLK8
(A)
TMS320DM6467T
www.ti.com
SPRS605C JULY 2009REVISED JUNE 2012
(A) For the -1G device, use an external clock source for the 54-/74.25-/108-/148.5-MHz VPIF clock.
Figure 7-37. VPIF Display Channel 3 Source Clock Selection
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 221
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T