Datasheet

A1
A1
T
T
FH
FL
DDR2
Controller
DM646x
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-42. DQS and DQ Routing Specification
(1)
No. Parameter Min Typ Max Unit
1 Center to center DQS-DQS spacing 2w
2 DQS E Skew Length Mismatch 25 Mils
3 Center to center DQS to other DDR2 trace spacing
(2)
4w
4 DQS/DQ nominal trace length
(1) (3) (4) (5)
DQLM-50 DQLM DQLM+50 Mils
5 DQ to DQS Skew Length Mismatch
(3) (4) (5)
100 Mils
6 DQ to DQ Skew Length Mismatch
(3) (4) (5)
100 Mils
7 DQ to DQ/DQS via count mismatch
(3) (4) (5)
1 Vias
8 Center to center DQ to other DDR2 trace spacing
(2) (6)
4w
9 Center to center DQ to other DQ trace spacing
(2) (7) (8)
3w
10 DQ/DQS E Skew Length Mismatch
(3) (4) (5)
100 Mils
(1) Series terminator, if used, should be located closest to DDR.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) A 16 bit DDR memory system will have two sets of data net classes, one for data byte 0, and one for data byte 1, each with an
associated DQS (2 DQS's).
(4) A 32 bit DDR memory system will have four sets of data net classes, one each for data bytes 0 through 3, and each associated with a
DQS (4 DQS's).
(5) There is no need and it is not recommended to skew match across data bytes, ie from DQS0 and data byte 0 to DQS1 and data byte 1.
(6) DQ's from other DQS domains are considered other DDR2 trace.
(7) DQ's from other data bytes are considered other DDR2 trace.
(8) DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.
Figure 7-33 shows the routing for the DQGATE net classes. Table 7-43 contains the routing specification.
Figure 7-33. DQGATE Routing
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 217
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