Datasheet

A1
A1
E0
T
E1
T
E2
DM646x
E3
T
DDR2
Controller
T
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 7-41. CK and ADDR_CTRL Routing Specification
(1)
No Parameter Min Typ Max Unit
1 Center to center CK-CK spacing 2w
2 CK A to B/A to C Skew Length Mismatch
(1)
25 Mils
3 CK B to C Skew Length Mismatch 25 Mils
4 Center to center CK to other DDR2 trace spacing
(2)
4w
5 CK/ADDR_CTRL nominal trace length
(3)
CACLM-50 CACLM CACLM+50 Mils
6 ADDR_CTRL to CK Skew Length Mismatch 100 Mils
7 ADDR_CTRL to ADDR_CTRL Skew Length Mismatch 100 Mils
8 Center to center ADDR_CTRL to other DDR2 trace spacing
(2)
4w
9 Center to center ADDR_CTRL to other ADDR_CTRL trace spacing
(2)
3w
10 ADDR_CTRL A to B/A to C Skew Length Mismatch
(1)
100 Mils
11 ADDR_CTRL B to C Skew Length Mismatch 100 Mils
(1) Series terminator, if used, should be located closest to DSP.
(2) Center to center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing
congestion.
(3) CACLM is the longest Manhattan distance of the CK and ADDR_CTRL net classes.
Figure 7-32 shows the topology and routing for the DQS and DQ net classes; the routes are point to point.
Skew matching across bytes is not needed nor recommended.
Figure 7-32. DQS and DQ Routing and Toplogy
216 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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