Datasheet

A1
A1
C B
A
T
DDR2
Controller
DM646x
DM646x
Device
A1
A1
DDR2Device
VREFNominalMinimum
TraceWidthis20Mils
VREFBypassCapacitor
NeckdowntominimuminBGA escape
regionsisacceptable.Narrowingto
accomodateviacongestionforshort
distancesisalsoacceptable.Best
performanceisobtainedifthewidth
ofVREFismaximized.
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.10.2.10 VREF Routing
VREF is used as a reference by the input buffers of the DDR2 memories as well as the DM6467T’s. VREF
is intended to be 1/2 the DDR2 power supply voltage and should be created using a resistive divider as
shown in Figure 7-27. Other methods of creating VREF are not recommended. Figure 7-30 shows the
layout guidelines for VREF.
Figure 7-30. VREF Routing and Topology
7.10.2.11 DDR2 CK and ADDR_CTRL Routing
Figure 7-31 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a
balanced T as it is intended that the length of segments B and C be equal. In addition, the length of A
should be maximized.
Figure 7-31. CK and ADDR_CTRL Routing and Topology
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 215
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