Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.10.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 7-36 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DSP and DDR2 interfaces. Additional bulk bypass
capacitance may be needed for other circuitry.
Table 7-36. Bulk Bypass Capacitors
No. Parameter Min Max Unit
1 DV
DD18
Bulk Bypass Capacitor Count
(1)
3 Devices
2 DV
DD18
Bulk Bypass Total Capacitance 30 μF
3 DDR#1 Bulk Bypass Capacitor Count
(1)
1 Devices
4 DDR#1 Bulk Bypass Total Capacitance
(1)
10 μF
5 DDR#2 Bulk Bypass Capacitor Count
(2)
1 Devices
6 DDR#2 Bulk Bypass Total Capacitance
(1) (2)
10 μF
(1) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed
(HS) bypass caps.
(2) Only used on 32-bit wide DDR2 memory systems
7.10.2.7 High-Speed Bypass Capacitors
High-Speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass cap, DSP/DDR power, and
DSP/DDR ground connections. Table 7-37 contains the specification for the HS bypass capacitors as well
as for the power connections on the PCB.
7.10.2.8 Net Classes
Table 7-38 lists the clock net classes for the DDR2 interface. Table 7-39 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 7-37. High-Speed Bypass Capacitors
No. Parameter Min Max Unit
1 HS Bypass Capacitor Package Size
(1)
0402 10 Mils
2 Distance from HS bypass capacitor to device being bypassed 250 Mils
3 Number of connection vias for each HS bypass capacitor
(2)
2 Vias
4 Trace length from bypass capacitor contact to connection via 1 30 Mils
5 Number of connection vias for each DSP device power or ground balls 1 Vias
6 Trace length from DSP device power ball to connection via 35 Mils
7 Number of connection vias for each DDR2 device power or ground balls 1 Vias
8 Trace length from DDR2 device power ball to connection via 35 Mils
9 DV
DD18
HS Bypass Capacitor Count
(3)
20 Devices
10 DV
DD18
HS Bypass Capacitor Total Capacitance 1.2 μF
11 DDR#1 HS Bypass Capacitor Count
(3)
8 Devices
12 DDR#1 HS Bypass Capacitor Total Capacitance 0.4 μF
13 DDR#2 HS Bypass Capacitor Count
(3) (4)
8 Devices
14 DDR#2 HS Bypass Capacitor Total Capacitance
(4)
0.4 μF
(1) LxW, 10 mil units, i.e., a 0402 is a 40x20 mil surface mount capacitor
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Only used on 32-bit wide DDR2 memory systems
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 213
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T