Datasheet

A1
A1
DDR2Controller
DDR2Device
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 7-35. Placement Specifications
No. Parameter Min Max Unit
1 X
(1) (2)
1660 Mils
2 Y
(1) (2)
1280 Mils
3 Y Offset
(1) (2) (3)
650 Mils
4 DDR2 Keepout Region
(4)
5 Clearance from non-DDR2 signal to DDR2 Keepout Region
(5)
4 w
(1) See Figure 7-26 for dimension defintions.
(2) Measurements from center of DSP device to center of DDR2 device.
(3) For 16 bit memory systems it is recommended that Y Offset be as small as possible.
(4) DDR2 Keepout region to encompass entire DDR2 routing area
(5) Non-DDR2 signals allowed within DDR2 keepout region provided they are separated from DDR2 routing layers by a ground plane.
7.10.2.5 DDR2 Keep Out Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2 keep
out region is defined for this purpose and is shown in Figure 7-29. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keep out region are shown in Table 7-
35.
Figure 7-29. DDR2 Keepout Region
NOTE
The region shown in Figure 7-29 should encompass all the DDR2 circuitry and varies
depending on placement. Non-DDR2 signals should not be routed on the DDR signal layers
within the DDR2 keep out region. Non-DDR2 signals may be routed in the region provided
they are routed on layers separated from DDR2 signal layers by a ground layer. No breaks
should be allowed in the reference ground layers in this region. In addition, the 1.8-V power
plane should cover the entire keep out region.
212 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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