Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 3-3. Memory Map Summary (continued)
MASTER PERIPHERAL ACCESSIBILITY
(1)
START END SIZE EDMA/
ARM C64x+
Video TSIF
ADDRESS ADDRESS (Bytes) PERIPHERAL
VDCE EMAC HPI PCI USB VLYNQ ATA
Port (0/1)
0x11F0 0000 0x11F0 7FFF 32K L1D RAM/Cache L1D RAM/Cache L1D RAM/Cache x x x x x
0x11F0 8000 0x11FF FFFF 992K Reserved Reserved Reserved
0x1200 0000 0x1FFF FFFF 224M
0x2000 0000 0x2000 7FFF 32K DDR2 Control DDR2 Control DDR2 Control
x
Registers Registers Registers
0x2000 8000 0x2000 FFFF 32K EMIFA Control EMIFA Registers EMIFA Registers
Registers
0x2001 0000 0x2001 7FFF 32K VLYNQ Control VLYNQ Registers VLYNQ Registers
Registers
0x2001 8000 0x200F FFFF 928K Reserved Reserved Reserved
0x2010 0000 0x2FFF FFFF 255M
0x3000 0000 0x3FFF FFFF 256M PCI Data PCI Data
0x4000 0000 0x403F FFFF 4M Reserved Reserved Reserved
0x4040 0000 0x4043 FFFF 256K
0x4044 0000 0x4047 FFFF 256K
0x4048 0000 0x404B FFFF 256K
0x404C 0000 0x404F FFFF 256K
0x4050 0000 0x405F FFFF 1M
0x4060 0000 0x4063 FFFF 256K Reserved Reserved Reserved
0x4064 0000 0x4067 FFFF 256K
0x4068 0000 0x406B FFFF 256K
0x406C 0000 0x406F FFFF 256K
0x4070 0000 0x41FF FFFF 25M
0x4200 0000 0x43FF FFFF 32M EMIFA Data (CS2)
(4)
EMIFA Data (CS2)
(4)
EMIFA Data (CS2)
(4)
x x x x
0x4400 0000 0x45FF FFFF 32M EMIFA Data (CS3)
(4)
EMIFA Data (CS3)
(4)
EMIFA Data (CS3)
(4)
x x x x
0x4600 0000 0x47FF FFFF 32M EMIFA Data (CS4)
(4)
EMIFA Data (CS4)
(4)
EMIFA Data (CS4)
(4)
x x x x
0x4800 0000 0x49FF FFFF 32M EMIFA Data (CS5)
(4)
EMIFA Data (CS5)
(4)
EMIFA Data (CS5)
(4)
x x x x
0x4A00 0000 0x4BFF FFFF 32M Reserved Reserved Reserved
0x4C00 0000 0x4FFF FFFF 64M VLYNQ (Remote Data) VLYNQ (Remote Data) VLYNQ (Remote Data) x x x x x x x
0x5000 0000 0x7FFF FFFF 768M Reserved Reserved Reserved
0x8000 0000 0x9FFF FFFF 512M DDR2 Memory DDR2 Memory DDR2 Memory x x x x x x x x x
0xA000 0000 0xBFFF FFFF 512M Reserved Reserved Reserved
0xC000 0000 0xFFFF FFFF 1G Reserved Reserved Reserved
(4) EMIFA CS0 and CS1 are not functionally supported on the DM6467T, and therefore, are not pinned out.
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