Datasheet

DDR_CLK
1
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.10.1 DDR2 Memory Controller Electrical Data/Timing
TI only supports board designs that follow the guidelines outlined in this document.
Table 7-31. Switching Characteristics Over Recommended Operating Conditions for DDR2 Memory
Controller
(1) (2)
(see Figure 7-25)
-1G
NO. PARAMETER UNIT
MIN MAX
1 t
c(DDR_CLK)
Cycle time, DDR_CLK 2.5 8 ns
2 f
(DDR_CLK)
Frequency, DDR_CLK 125 400 MHz
(1) DDR_CLK cycle time = 2 x PLL2 _SYSCLK1 cycle time.
(2) The PLL2 Controller must be programmed such that the resulting DDR_CLK clock frequency is within the specified range.
Figure 7-25. DDR2 Memory Controller Clock Timing
7.10.2 DDR2 Interface
This section provides the timing specification for the DDR2 interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see Understanding TI’s PCB Routing Rule-Based DDR2 Timing Specification Application
Report (SPRAAV0).
7.10.2.1 DDR2 Interface Schematic
Figure 7-26 shows the DDR2 interface schematic for a x32 DDR2 memory system. The x16 DDR2 system
schematic is identical except that the high word DDR2 device is deleted, see Figure 7-27. The pin
numbers for the DM6467T can be obtained from the Section 3.6, Pin Assignments of this document.
7.10.2.2 Compatible JEDEC DDR2 Devices
Table 7-32 shows the parameters of the JEDEC DDR2 devices that are compatible with this interface.
Generally, the DDR2 interface is compatible with x16 DDR2-800 speed grade DDR2 devices.
Table 7-32. Compatible JEDEC DDR2 Devices
No. Parameter Min Max Unit
1 JEDEC DDR2 Device Speed Grade
(1)
DDR2-800
2 JEDEC DDR2 Device Bit Width x16 x16 Bits
3 JEDEC DDR2 Device Count
(2)
1 2 Devices
4 JEDEC DDR2 Device Ball Count
(3)
84 92 Balls
(1) Higher DDR2 speed grades are supported due to inherent JEDEC DDR2 backwards compatibility.
(2) 1 DDR2 device is used for 16 bit DDR2 memory system. 2 DDR2 devices are used for 32 bit DDR2 memory system.
(3) 92 ball devices retained for legacy support. New designs will migrate to 84 ball DDR2 devices. Electrrically the 92 and 84 ball DDR2
devices are the same.
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