Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
7.10 DDR2 Memory Controller
The DDR2 Memory Controller is a dedicated interface to DDR2 SDRAM. It supports JESD79D-2A
standard compliant DDR2 SDRAM devices and can interface to either 16-bit or 32-bit DDR2 SDRAM
devices. For details on the DDR2 Memory Controller, see the TMS320DM646x DMSoC DDR2 Memory
Controller User's Guide (literature number SPRUEQ4).
A memory map of the DDR2 Memory Controller registers is shown in Table 7-30.
Table 7-30. DDR2 Memory Controller Registers
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C4 004C – Reserved
0x01C4 2038 – Reserved
0x2000 0000 - 0x2000 0003 – Reserved
0x2000 0004 SDRSTAT SDRAM Status Register
0x2000 0008 SDBCR SDRAM Bank Configuration Register
0x2000 000C SDRCR SDRAM Refresh Control Register
0x2000 0010 SDTIMR SDRAM Timing Register 1
0x2000 0014 SDTIMR2 SDRAM Timing Register 2
0x2000 0018 - 0x2000 001F – Reserved
0x2000 0020 PBBPR Peripheral Bus Burst Priority Register
0x2000 0024 - 0x2000 00BF – Reserved
0x2000 00C0 IRR Interrupt Raw Register
0x2000 00C4 IMR Interrupt Masked Register
0x2000 00C8 IMSR Interrupt Mask Set Register
0x2000 00CC IMCR Interrupt Mask Clear Register
0x2000 00D0 - 0x2000 00E3 – Reserved
0x2000 00E4 DDRPHYCR DDR2 PHY Control Register
0x2000 00E8 - 0x2000 00EF – Reserved
0x2000 00F0 VTPIOCR DDR2 VTP IO Control Register
0x2000 00F4 - 0x2000 7FFF – Reserved
206 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T