Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
Table 7-29. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for EMIFA Module
(1) (2)
(see Figure 7-21 and Figure 7-22)
-1G
NO. PARAMETER UNIT
MIN MAX
READS and WRITES
1 t
d(TURNAROUND)
Turn around time (TA + 1) * E - 3 (TA + 1) * E + 3 ns
READS
(RS + RST + RH + (RS + RST + RH + TA +
EMIF read cycle time (EW = 0) ns
TA + 4) * E - 3 4) * E + 3
3 t
c(EMRCYCLE)
(RS + RST + RH +
EMIF read cycle time (EW = 1) 4184 * E + 3 ns
TA + 4) * E - 3
Output setup time, EM_CS[5:2] low to EM_OE low
(RS + 1) * E - 3 (RS + 1) * E + 3 ns
(SS = 0)
4 t
su(EMCSL-EMOEL)
Output setup time, EM_CS[5:2] low to EM_OE low
3 ns
(SS = 1)
Output hold time, EM_OE high to EM_CS[5:2] high
(RH + 1) * E - 3 (RH + 1) * E + 3 ns
(SS = 0)
5 t
h(EMOEH-EMCSH)
Output hold time, EM_OE high to EM_CS[5:2] high
3 ns
(SS = 1)
6 t
su(EMBAV-EMOEL)
Output setup time, EM_BA[1:0] valid to EM_OE low (RS + 1) * E - 3 (RS + 1) * E + 3 ns
7 t
h(EMOEH-EMBAIV)
Output hold time, EM_OE high to EM_BA[1:0] invalid (RH + 1) * E - 3 (RH + 1) * E + 3 ns
8 t
su(EMBAV-EMOEL)
Output setup time, EM_A[22:0] valid to EM_OE low (RS + 1) * E - 3 (RS + 1) * E + 3 ns
9 t
h(EMOEH-EMBAIV)
Output hold time, EM_OE high to EM_A[22:0] invalid (RH + 1) * E - 3 (RH + 1) * E + 3 ns
EM_OE active low width (EW = 0) (RST + 1) * E - 3 (RST + 1) * E + 3 ns
10 t
w(EMOEL)
EM_OE active low width (EW = 1) (RST + 1) * E - 3 (RST + 4097) * E + 3 ns
11 t
d(EMWAITH-EMOEH)
Delay time from EM_WAITx deasserted to EM_OE high 4E + 3 ns
WRITES
(WS + WST + WH (WS + WST + WH + TA
EMIF write cycle time (EW = 0) ns
+ TA + 4) * E - 3 + 4) * E + 3
15 t
c(EMWCYCLE)
(WS + WST + WH
EMIF write cycle time (EW = 1) 4184 * E + 3 ns
+ TA + 4) * E - 3
Output setup time, EM_CS[5:2] low to EM_WE low
(WS + 1) * E - 3 (WS + 1) * E + 3 ns
(SS = 0)
16 t
su(EMCSL-EMWEL)
Output setup time, EM_CS[5:2] low to EM_WE low
3 ns
(SS = 1)
Output hold time, EM_WE high to EM_CS[5:2] high
(WH + 1) * E - 3 (WH + 1) * E + 3 ns
(SS = 0)
17 t
h(EMWEH-EMCSH)
Output hold time, EM_WE high to EM_CS[5:2] high
3 ns
(SS = 1)
18 t
su(EMRNW-EMWEL)
Output setup time, EM_R/W valid to EM_WE low (WS + 1) * E - 3 (WS + 1) * E + 3 ns
19 t
h(EMWEH-EMRNW)
Output hold time, EM_WE high to EM_R/W invalid (WH + 1) * E - 3 (WH + 1) * E + 3 ns
20 t
su(EMBAV-EMWEL)
Output setup time, EM_BA[1:0] valid to EM_WE low (WS + 1) * E - 3 (WS + 1) * E + 3 ns
21 t
h(EMWEH-EMBAIV)
Output hold time, EM_WE high to EM_BA[1:0] invalid (WH + 1) * E - 3 (WH + 1) * E + 3 ns
22 t
su(EMAV-EMWEL)
Output setup time, EM_A[22:0] valid to EM_WE low (WS + 1) * E - 3 (WS + 1) * E + 3 ns
23 t
h(EMWEH-EMAIV)
Output hold time, EM_WE high to EM_A[22:0] invalid (WH + 1) * E - 3 (WH + 1) * E + 3 ns
EM_WE active low width (EW = 0) (WST + 1) * E - 3 (WST + 1) * E + 3 ns
24 t
w(EMWEL)
EM_WE active low width (EW = 1) (WST + 1) * E - 3 (WST + 4097) * E + 3 ns
25 t
d(EMWAITH-EMWEH)
Delay time from EM_WAITx deasserted to EM_WE high 4E + 3 ns
26 t
su(EMDV-EMWEL)
Output setup time, EM_D[15:0] valid to EM_WE low (WS + 1) * E - 3 (WS + 1) * E + 3 ns
(1) RS = Read setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold, TA = Turn Around,
EW = Extend Wait mode, SS = Select Strobe mode. These parameters are programmed via the Asynchronous n Configuration and the
Asynchronous Wait Cycle Configuration registers and support the following range of values: TA[0–3], RS[0–15], RST[0–63], RH[0–7],
WS[0–15], WST[0–63], WH[0–7], EW[0–1], and MEWC[0–255]. For more information, see the TMS320DM646x DMSoC Asynchronous
External Memory Interface (EMIF) User's Guide (literature number SPRUEQ7).
(2) E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 1 GHz, use E = 4 ns.
202 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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