Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.9.4 EMIFA Electrical Data/Timing
Table 7-28. Timing Requirements for Asynchronous Memory Cycles for EMIFA Module
(1)
(see Figure 7-21 and Figure 7-22)
-1G
NO. UNIT
MIN MAX
READS and WRITES
2 t
w(EM_WAIT)
Pulse duration, EM_WAITx assertion and deassertion 2E ns
READS
12 t
su(EMDV-EMOEH)
Setup time, EM_D[15:0] valid before EM_OE high 5 ns
13 t
h(EMOEH-EMDIV)
Hold time, EM_D[15:0] valid after EM_OE high 0 ns
14 t
su (EMWAIT-EMOEH)
Setup time, EM_WAITx asserted before EM_OE high
(2)
4E + 3 ns
WRITES
28 t
su(EMWAIT-EMWEH)
Setup time, EM_WAITx asserted before EM_WE high
(2)
4E + 3 ns
(1) E = SYSCLK3 period in ns for EMIFA. For example, when running the DSP CPU at 1 GHz, use E = 4 ns.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAITx must be asserted to add extended
wait states. Figure 7-23 and Figure 7-24 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 201
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