Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 3-3. Memory Map Summary
MASTER PERIPHERAL ACCESSIBILITY
(1)
START END SIZE EDMA/
ARM C64x+
Video TSIF
ADDRESS ADDRESS (Bytes) PERIPHERAL
VDCE EMAC HPI PCI USB VLYNQ ATA
Port (0/1)
0x0000 0000 0x0000 3FFF 16K ARM RAM0
(Instruction)
0x0000 4000 0x0000 7FFF 16K ARM RAM1
(Instruction)
0x0000 8000 0x0000 FFFF 32K ARM ROM (Instruction)
0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data)
0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data)
0x0001 8000 0x0001 FFFF 32K ARM ROM (Data)
Reserved Reserved
0x0002 0000 0x000F FFFF 896K
0x0010 0000 0x003F FFFF 3M
0x0040 0000 0x004F FFFF 1M
0x0050 0000 0x005F FFFF 1M Reserved
0x0060 0000 0x006F FFFF 1M
0x0070 0000 0x007F FFFF 1M
0x0080 0000 0x0080 FFFF 64K
0x0081 0000 0x0081 7FFF 32K Reserved Hole (MPPA Disable)
(2)
Reserved
0x0081 8000 0x0083 7FFF 128K L2 RAM/Cache
0x0083 8000 0x008F FFFF 800K Reserved
0x0090 0000 0x0092 FFFF 192K
0x0093 0000 0x009F FFFF 832K
0x00A0 0000 0x00DF FFFF 4M
Reserved
0x00E0 0000 0x00E0 7FFF 32K L1P RAM/Cache
0x00E0 8000 0x00EF FFFF 992K Reserved
0x00F0 0000 0x00F0 7FFF 32K L1D RAM/Cache Reserved
0x00F0 8000 0x017F FFFF 9184K Reserved
0x0180 0000 0x01BB FFFF 3840K
0x01BC 0000 0x01BC 0FFF 4K ARM ETB Memory
0x01BC 1000 0x01BC 17FF 2K ARM ETB Registers
CFG Space
0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher
0x01BC 1900 0x01BC 1BFF 768 Reserved
0x01BC 1C00 0x01BF FFFF 249K
0x01C0 0000 0x0FFF FFFF 228M CFG Bus Peripherals CFG Bus Peripherals CFG Bus Peripherals x
(3)
x
(3)
x
(3)
0x1000 0000 0x1000 FFFF 64K Reserved
0x1001 0000 0x1001 3FFF 16K ARM RAM0 (Data) ARM RAM0 (Data) x x x x x x x
0x1001 4000 0x1001 7FFF 16K ARM RAM1 (Data) ARM RAM1 (Data) x x x x x x x
0x1001 8000 0x1001 FFFF 32K ARM ROM (Data) ARM ROM (Data) x x x x x x x
0x1002 0000 0x10FF FFFF 16256K
0x1100 0000 0x113F FFFF 4M Reserved
0x1140 0000 0x114F FFFF 1M
0x1150 0000 0x115F FFFF 1M Reserved Reserved
0x1160 0000 0x116F FFFF 1M
0x1170 0000 0x117F FFFF 1M
0x1180 0000 0x1180 FFFF 64K
0x1181 0000 0x1181 7FFF 32K Reserved Hole (MPPA Disable)
(2)
Reserved
0x1181 8000 0x1183 7FFF 128K L2 RAM/Cache L2 RAM/Cache L2 RAM/Cache x x x x x x
0x1183 8000 0x118F FFFF 800K Reserved Reserved Reserved
0x1190 0000 0x11DF FFFF 5M
0x11E0 0000 0x11E0 7FFF 32K L1P RAM/Cache L1P RAM/Cache L1P RAM/Cache x x x x x
0x11E0 8000 0x11EF FFFF 992K Reserved Reserved Reserved
(1) These peripherals have their own DMA engine or master port interface to the DMSoC system bus and do not use the EDMA for data
transfers. The x symbol indicates that the peripheral has a valid connection through the device switch fabric to the memory region
identified in the EDMA access column.
(2) MPPA should be used to disable the hole. For more information on MPPA, see the TMS320C64x+ DSP Megamodule Reference Guide
(SPRU871).
(3) The HPI's, PCI's, and VLYNQ's access to the configuration bus peripherals is limited, see Table 3-4, Configuration Memory Map
Summary for the details.
20 Device Overview Copyright © 2009–2012, Texas Instruments Incorporated
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