Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
• External Memory Interfaces (EMIFs) – SIR and MIR (0.576 MBAUD)
– Up to 400-MHz 32-Bit DDR2 SDRAM Memory – CIR With Programmable Data Encoding
Controller With 512M-Byte Address Space
• One Serial Peripheral Interface (SPI) With Two
(1.8-V I/O)
Chip-Selects
– Asynchronous16-Bit Wide EMIF (EMIFA)
• Master/Slave Inter-Integrated Circuit (I
2
C Bus™)
With 128M-Byte Address Reach
• Two Multichannel Audio Serial Ports (McASPs)
• Flash Memory Interfaces
– One Four Serializer Transmit/Receive Port
– NOR (8-/16-Bit-Wide Data)
– One Single DIT Transmit Port for S/PDIF
– NAND (8-/16-Bit-Wide Data)
• 32-Bit Host Port Interface (HPI)
• Enhanced Direct-Memory-Access (EDMA)
• VLYNQ™ Interface (FPGA Interface)
Controller (64 Independent Channels)
• Two Pulse Width Modulator (PWM) Outputs
– Programmable Default Burst Size
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
• Up to 33 General-Purpose I/O (GPIO) Pins
– IEEE 802.3 Compliant (3.3-V I/O Only)
(Multiplexed With Other Device Functions)
– Supports MII and GMII Media Independent
• On-Chip ARM ROM Bootloader (RBL)
Interfaces
• Individual Power-Saving Modes for ARM/DSP
– Management Data I/O (MDIO) Module
• Flexible PLL Clock Generators
• USB Port With Integrated 2.0 PHY
• IEEE-1149.1 (JTAG) Boundary-
– USB 2.0 High-/Full-Speed Client
Scan-Compatible
– USB 2.0 High-/Full-/Low-Speed Host
• 529-Pin Pb-Free BGA Package
(Mini-Host, Supporting One External
(CUT Suffix), 0.8-mm Ball Pitch
Device)
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 32-Bit, 66-MHz, 3.3 V Peripheral Component
• 3.3-V and 1.8-V I/O, 1.3-V Internal
Interconnect (PCI) Master/Slave Interface
• Applications:
– Conforms to PCI Specification 2.3
– Video Encode/Decode/Transcode/Transrate
• Two 64-Bit General-Purpose Timers (Each
– Digital Media
Configurable as Two 32-Bit Timers)
– Networked Media Encode/Decode
• One 64-Bit Watch Dog Timer
– Video Imaging
• Three Configurable UART/IrDA/CIR Modules
– Video Infrastructure
(One With Modem Control Signals)
– Video Conferencing
– Supports up to 1.8432 Mbps UART
2 Digital Media System-on-Chip (DMSoC) Copyright © 2009–2012, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T