Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
7.7.9 Reset Electrical Data/Timing
Note: If a configuration pin must be routed out from the device, the internal pullup/pulldown (IPU/IPD)
resistor should not be relied upon; TI recommends the use of an external pullup/pulldown resistor.
Table 7-21. Timing Requirements for Reset (see Figure 7-19 and Figure 7-20)
-1G
NO. UNIT
MIN MAX
1 t
w(RESET)
Pulse duration, POR low or RESET low 12C
(1)
ns
Setup time, boot and configuration pins valid before POR high or RESET
2 t
su(CONFIG)
12C
(1)
ns
high
(2)
Hold time, boot and configuration pins valid after POR high or RESET
3 t
h(CONFIG)
0 ns
high
(2)
(1) C = 1/DEV_MXI clock frequency in ns. The device clock source must be stable and at a valid frequency prior to meeting the t
w(RESET)
requirement.
(2) For the list of boot and configuration pins, see Table 3-5, Boot Terminal Functions.
Table 7-22. Switching Characteristics Over Recommended Operating Conditions During Reset
(1)
(see Figure 7-20)
-1G
NO. PARAMETER UNIT
MIN MAX
4 t
w(PAUSE)
Pulse duration, SYSCLKs paused (low) 10C 10C ns
23 t
d(RSTH-PAUSE)
Delay time, RESET high or POR high to SYSCLKs paused (low) 1990C ns
5 t
d(RSTL-BOOTZ)
Delay time, RESET low to Boot Configuration Group high impedance 0 20 ns
6 t
d(RSTL-DDRZZ)
Delay time, RESET low to DDR2 Z Group high impedance 0 7P + 20 ns
7 t
d(RSTL-DDRLL)
Delay time, RESET low to DDR2 Low Group low 0 3P + 20 ns
8 t
d(RSTL-DDRHH)
Delay time, RESET low to DDR2 High Group high 0 20 ns
13 t
d(RSTL-DDRZHZ)
Delay time, RESET low to DDR2 Z/High Group high impedance 0 7P + 20 ns
14 t
d(RSTL-DDRLHL)
Delay time, RESET low to DDR2 Low/High Group low 0 20 ns
17 t
d(RSTL-ZZ)
Delay time, RESET low to Z Group high impedance 0 20 ns
18 t
d(RSTL-LOWL)
Delay time, RESET low to Low Group low 0 20 ns
19 t
d(RSTL-HIGHH)
Delay time, RESET low to High Group high 0 20 ns
9 t
d(RSTL-BOOTV)
Delay time, RESET high to Boot Configuration Group valid
(2)
ns
10 t
d(RSTH-DDRZV)
Delay time, RESET high to DDR2 Z Group valid
(2)
ns
11 t
d(RSTH-DDRLV)
Delay time, RESET high to DDR2 Low Group valid
(2)
ns
12 t
d(RSTH-DDRHV)
Delay time, RESET high to DDR2 High Group valid
(2)
ns
15 t
d(RSTH-DDRZHV)
Delay time, RESET high to DDR2 Z/High Group valid high
(2)
ns
16 t
d(RSTH-DDRLHV)
Delay time, RESET high to DDR2 Low/High Group valid high
(2)
ns
20 t
d(RSTH-ZV)
Delay time, RESET high to Z Group valid
(2)
ns
21 t
d(RSTH-LOWV)
Delay time, RESET high to Low Group valid
(2)
ns
22 t
d(RSTH-HIGHV)
Delay time, RESET high to High Group valid
(2)
ns
(1) C = 1/DEV_CLKIN clock frequency in ns.
(2) Following RESET high or POR high, this signal group maintains the state the pins(s) achieved while RESET or POR was driven low until
the peripheral is enabled via the PSC. For example, the DDR2 Z Group goes high impedance following RESET low or POR low and
remains in the high-impedance state following RESET high or POR high until the DDR2 controller is enabled via the PSC.
Figure 7-19 shows the Power-Up Timing. Figure 7-20 shows the Warm Reset (RESET) Timing. Max Reset
Timing is identical to Warm Reset Timing, except the boot and configuration pins are not relatched and
the BOOTCFG register retains its previous value latched before the Max Reset was initiated.
190 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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