Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Default Power Down Pins
As discussed in Section 4.2, Power Considerations, the VDD3P3V_PWDN register controls power to the
3.3-V pins. The VDD3P3V_PWDN register defaults to powering down some 3.3-V pins to save power. For
more details on the VDD3P3V_PWDN register and which 3.3-V pins default to power up or power down,
see Section 4.2, Power Considerations. The pins that default to power down, are both reset to power
down and high-impedance. They remain in that state until configured otherwise by VDD3P3_PWDN and
PINMUX0/PINMUX1 programming.
• Default Power Down Pin Group: USB_DRVVBUS/GP[22], CLKOUT0, SPI_CLK, SPI_EN, SPI_CS0,
SPI_CS1, SPI_MISO, SPI_MOSI, VLYNQ_CLOCK, VLYNQ_SCRUN, VLYNQ_TXD[3:0],
VLYNQ_RXD[3:0], RFTCLK, GMTCLK, MTXD[7:4], MRXD[7:4], MTCLK, MTXD[3:0], MTXEN, MCOL,
MCRS, MRCLK, MRXD[3:0], MRXDV, MRXER, MDCLK, MDIO, ACLKX1, AHCLKX1, AXR1[0],
ACLKR0, AHCLKR0, AFSR0, ACLKX0, AHCLKX0, AFSX0, AXR0[3:0], AMUTE0, AMUTEIN0,
PCI_CLK/GP[10], PCI_DEVSEL/HCNTL1/EM_BA[1], PCI_FRAME/HINT/EM_BA[0],
PCI_IRDY/HRDY/EM_A[17], PCI_TRDY/HHWIL/EM_A[16], PCI_STOP/HCNTL0/EM_WE,
PCI_SERR/HDS1/EM_OE, PCI_PERR/HCS/EM_DQM1, PCI_PAR/HAS/EM_DQM0,
PCI_INTA/EM_WAIT2, PCI_CBE3/HR/W/EM_CS3, PCI_CBE2/HDS2/EM_CS2,
PCI_AD[15:0]/HD[15:0]/EM_D[15:0], PCI_RST/DA2/GP[13]/EM_A[22], PCI_IDSEL/HDDIR/EM_R/W,
PCI_REQ/DMARQ/GP[11]/EM_CS5, PCI_GNT/DMACK/GP[12]/EM_CS4,
PCI_CBE1/ATA_CS1/GP[32]/EM_A[19], PCI_CBE0/ATA_CS0/GP[33]/EM_A[18],
DIOW/GP[20]/EM_WAIT4, IORDY/GP[21]/EM_WAIT3, DIOR/GP[19]/EM_WAIT5,
DA1/GP[16]/EM_A[21], DA0/GP[17]/EM_A[20], INTRQ/GP[18]/RSV ,
PCI_AD[31:16]/DD[15:0]/HD[31:16]/EM_A[15:0], GP[7], GP[6], GP[5], GP[4]/STC_CLKIN,
GP[3]/AUDIO_CLK0, GP[2]/AUDIO_CLK1, GP[1], GP[0], TOUT2, TINP1L, TOUT1L, TOUT1U,
TINP0L, TINP0U, TOUT0L, TOUT0U, PWM1/TS1_DOUT, PWM0/CRG0_PO/TS1_ENAO,
URTS2/UIRTX2/TS0_PSTIN/GP[41], UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PSTO,
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI, UTXD2/URCTX2/CRG1_PO/GP[40]/CRG0_PO,
URTS1/UIRTX1/TS0_WAITO/GP[25], UCTS1/USD1/TS0_EN_WAITO/GP[26],
URXD1/TS0_DIN7/GP[23], UTXD1/URCTX1/TS0_DOUT7/GP[24], UDTR0/TS0_ENAO/GP[36],
UDSR0/TS0_PSTO/GP[37], UDCD0/TS0_WAITIN/GP[38], URIN0/GP[8]/TS1_WAITIN,
URXD0/TS1_DIN, UTXD0/URCTX0/TS1_PSTIN, URTS0/UIRTX0/TS1_EN_WAITO, UCTS0/USD0,
VP_DOUT15/TS1_DIN, VP_DOUT14/TS1_PSTIN, VP_DOUT13/TS1_EN_WAITO,
VP_DOUT12/TS1_WAITO, VP_DOUT11/TS1_DOUT, VP_DOUT10/TS1_PSTO,
VP_DOUT9/TS1_ENAO, VP_DOUT8/TS1_WAITIN, VP_CLKIN3/TS1_CLKO, VP_CLKO3/TS0_CLKO,
VP_DOUT7, VP_DOUT6/DSPBOOT, VP_DOUT5/PCIEN, VP_DOUT4/CS2BW,
VP_DOUT3/BTMODE3, VP_DOUT2/BTMODE2, VP_DOUT1/BTMODE1, VP_DOUT0/BTMODE0,
VP_CLKIN2, VP_CLKO2, VP_DIN15_VSYNC/TS0_DIN7, VP_DIN14_HSYNC/TS0_DIN6,
VP_DIN13_FIELD/TS0_DIN5, VP_DIN12/TS0_DIN4, VP_DIN11/TS0_DIN3, VP_DIN10/TS0_DIN2,
VP_DIN9/TS0_DIN1, VP_DIN8/TS0_DIN0, VP_CLKIN1, VP_DIN7/TS0_DOUT7/TS1_DIN,
VP_DIN6/TS0_DOUT6/TS1_PSTIN, VP_DIN5/TS0_DOUT5/TS1_EN_WAITO,
VP_DIN4/TS0_DOUT4/TS1_WAITO, VP_DIN3/TS0_DOUT3, VP_DIN2/TS0_DOUT2,
VP_DIN1/TS0_DOUT1, VP_DIN0/TS0_DOUT0, VP_CLKIN0.
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 187
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