Datasheet

TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012 www.ti.com
4. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
– The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
– The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
– The PLL Controllers are operating in PLL Bypass Mode.
– The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. For more details on the boot sequence, see the
Using the TMS320DM646x Bootloader Application Report (literature number SPRAAS0).
7.7.3 Maximum Reset
A Maximum (Max) Reset is initiated by the emulator or the watchdog timer (Timer 2). The effects are the
same as a warm reset, except the device boot and configuration pins are not re-latched. The emulator
initiates a maximum reset via the ICEPICK module. This ICEPICK-initiated reset is non-maskable. When
the watchdog timer counter reaches zero, this will also initiate a maximum reset to recover from a runaway
condition.
To invoke the maximum reset via the ICEPICK module, the user can perform the following from the Code
Composer Studio™ IDE menu: Debug→Advanced Resets→System Reset
This is the Max Reset sequence:
1. Max Reset is initiated by the emulator or the watchdog timer.
During this time, the following happens:
– The reset signals flow to the entire chip, resetting all the modules on chip except the test and
emulation logic.
– The PLL Controllers are reset —thereby, switching back to PLL Bypass Mode and resetting all their
registers to default values. Both PLL1 and PLL2 are placed in reset and lose lock.
2. After device initialization is complete, the PLL Controllers pause the system clocks for 10 cycles.
At this point:
– The I/O pins are controlled by the default peripherals (default peripherals are determined by
PINMUX0 and PINMUX1 registers).
– The clock and reset of each peripheral is determined by the default settings of the Power and Sleep
Controller (PSC).
– The PLL Controllers are operating in PLL Bypass Mode.
– The ARM926 begins executing from the default address (either ARM boot ROM, TCM RAM, or
EMIFA).
After the reset sequence, the boot sequence begins. Since the boot and configuration pins are not latched
with a Max Reset, the previous values (as shown in the BOOTCFG register) are used to select the boot
mode. For more details on the boot sequence, see the Using the TMS320DM646x Bootloader Application
Report (literature number SPRAAS0).
7.7.4 System Reset
A System Reset is initiated by the emulator. The following memory contents are maintained:
• L1/L2 RAM: The C64x+ L1/L2 RAM content is retained. The L1/L2 cache content is not retained
because tag information is reset.
• DDR2 Memory Controller: The DDR2 Memory Controller registers are not reset. In addition, the DDR2
SDRAM memory content is retained if the user places the DDR2 SDRAM in self-refresh mode before
invoking the System Reset.
184 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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