Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information

TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-16. DM6467T EDMA Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C1 068C - 0x01C1 06FF – Reserved
0x01C1 0700 DFOPT0 EDMA3 TC1 Destination FIFO Options Register 0
0x01C1 0704 DFSRC0 EDMA3 TC1 Destination FIFO Source Address Register 0
0x01C1 0708 DFCNT0 EDMA3 TC1 Destination FIFO Count Register 0
0x01C1 070C DFDST0 EDMA3 TC1 Destination FIFO Destination Address Register 0
0x01C1 0710 DFBIDX0 EDMA3 TC1 Destination FIFO B-Index Register 0
0x01C1 0714 DFMPPRXY0 EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 0
0x01C1 0718 - 0x01C1 073F – Reserved
0x01C1 0740 DFOPT1 EDMA3 TC1 Destination FIFO Options Register 1
0x01C1 0744 DFSRC1 EDMA3 TC1 Destination FIFO Source Address Register 1
0x01C1 0748 DFCNT1 EDMA3 TC1 Destination FIFO Count Register 1
0x01C1 074C DFDST1 EDMA3 TC1 Destination FIFO Destination Address Register 1
0x01C1 0750 DFBIDX1 EDMA3 TC1 Destination FIFO B-Index Register 1
0x01C1 0754 DFMPPRXY1 EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 1
0x01C1 0758 - 0x01C1 077F – Reserved
0x01C1 0780 DFOPT2 EDMA3 TC1 Destination FIFO Options Register 2
0x01C1 0784 DFSRC2 EDMA3 TC1 Destination FIFO Source Address Register 2
0x01C1 0788 DFCNT2 EDMA3 TC1 Destination FIFO Count Register 2
0x01C1 078C DFDST2 EDMA3 TC1 Destination FIFO Destination Address Register 2
0x01C1 0790 DFBIDX2 EDMA3 TC1 Destination FIFO B-Index Register 2
0x01C1 0794 DFMPPRXY2 EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 2
0x01C1 0798 - 0x01C1 07BF – Reserved
0x01C1 07C0 DFOPT3 EDMA3 TC1 Destination FIFO Options Register 3
0x01C1 07C4 DFSRC3 EDMA3 TC1 Destination FIFO Source Address Register 3
0x01C1 07C8 DFCNT3 EDMA3 TC1 Destination FIFO Count Register 3
0x01C1 07CC DFDST3 EDMA3 TC1 Destination FIFO Destination Address Register 3
0x01C1 07D0 DFBIDX3 EDMA3 TC1 Destination FIFO B-Index Register 3
0x01C1 07D4 DFMPPRXY3 EDMA3 TC1 Destination FIFO Memory Protection Proxy Register 3
0x01C1 07D8 - 0x01C1 07FF – Reserved
Transfer Controller 2 Registers
0x01C1 0800 PID Peripheral Identification Register
0x01C1 0804 TCCFG EDMA3 TC2 Configuration Register
0x01C1 0808 - 0x01C1 08FF – Reserved
0x01C1 0900 TCSTAT EDMA3 TC2 Channel Status Register
0x01C1 0904 - 0x01C1 0913 – Reserved
0x01C1 0914 - 0x01C1 091F – Reserved
0x01C1 0920 ERRSTAT EDMA3 TC2 Error Status Register
0x01C1 0924 ERREN EDMA3 TC2 Error Enable Register
0x01C1 0928 ERRCLR EDMA3 TC2 Error Clear Register
0x01C1 092C ERRDET EDMA3 TC2 Error Details Register
0x01C1 0930 ERRCMD EDMA3 TC2 Error Interrupt Command Register
0x01C1 0934 - 0x01C1 093F – Reserved
0x01C1 0940 RDRATE EDMA3 TC2 Read Command Rate Register
0x01C1 0944 - 0x01C1 09FF – Reserved
0x01C1 0A00 - 0x01C1 0A3F – Reserved
0x01C1 0A40 SAOPT EDMA3 TC2 Source Active Options Register
0x01C1 0A44 SASRC EDMA3 TC2 Source Active Source Address Register
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