Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
Table 7-16. DM6467T EDMA Registers (continued)
HEX ADDRESS RANGE ACRONYM REGISTER NAME
0x01C0 0198 DCHMAP38 DMA Channel 38 Mapping to PaRAM Register
0x01C0 019C DCHMAP39 DMA Channel 39 Mapping to PaRAM Register
0x01C0 01A0 DCHMAP40 DMA Channel 40 Mapping to PaRAM Register
0x01C0 01A4 DCHMAP41 DMA Channel 41 Mapping to PaRAM Register
0x01C0 01A8 DCHMAP42 DMA Channel 42 Mapping to PaRAM Register
0x01C0 01AC DCHMAP43 DMA Channel 43 Mapping to PaRAM Register
0x01C0 01B0 DCHMAP44 DMA Channel 44 Mapping to PaRAM Register
0x01C0 01B4 DCHMAP45 DMA Channel 45 Mapping to PaRAM Register
0x01C0 01B8 DCHMAP46 DMA Channel 46 Mapping to PaRAM Register
0x01C0 01BC DCHMAP47 DMA Channel 47 Mapping to PaRAM Register
0x01C0 01C0 DCHMAP48 DMA Channel 48 Mapping to PaRAM Register
0x01C0 01C4 DCHMAP49 DMA Channel 49 Mapping to PaRAM Register
0x01C0 01C8 DCHMAP50 DMA Channel 50 Mapping to PaRAM Register
0x01C0 01CC DCHMAP51 DMA Channel 51 Mapping to PaRAM Register
0x01C0 01D0 DCHMAP52 DMA Channel 52 Mapping to PaRAM Register
0x01C0 01D4 DCHMAP53 DMA Channel 53 Mapping to PaRAM Register
0x01C0 01D8 DCHMAP54 DMA Channel 54 Mapping to PaRAM Register
0x01C0 01DC DCHMAP55 DMA Channel 55 Mapping to PaRAM Register
0x01C0 01E0 DCHMAP56 DMA Channel 56 Mapping to PaRAM Register
0x01C0 01E4 DCHMAP57 DMA Channel 57 Mapping to PaRAM Register
0x01C0 01E8 DCHMAP58 DMA Channel 58 Mapping to PaRAM Register
0x01C0 01EC DCHMAP59 DMA Channel 59 Mapping to PaRAM Register
0x01C0 01F0 DCHMAP60 DMA Channel 60 Mapping to PaRAM Register
0x01C0 01F4 DCHMAP61 DMA Channel 61 Mapping to PaRAM Register
0x01C0 01F8 DCHMAP62 DMA Channel 62 Mapping to PaRAM Register
0x01C0 01FC DCHMAP63 DMA Channel 63 Mapping to PaRAM Register
0x01C0 0200 QCHMAP0 QDMA Channel 0 Mapping to PaRAM Register
0x01C0 0204 QCHMAP1 QDMA Channel 1 Mapping to PaRAM Register
0x01C0 0208 QCHMAP2 QDMA Channel 2 Mapping to PaRAM Register
0x01C0 020C QCHMAP3 QDMA Channel 3 Mapping to PaRAM Register
0x01C0 0210 QCHMAP4 QDMA Channel 4 Mapping to PaRAM Register
0x01C0 0214 QCHMAP5 QDMA Channel 5 Mapping to PaRAM Register
0x01C0 0218 QCHMAP6 QDMA Channel 6 Mapping to PaRAM Register
0x01C0 021C QCHMAP7 QDMA Channel 7 Mapping to PaRAM Register
0x01C0 0220 - 0x01C0 023F – Reserved
0x01C0 0240 DMAQNUM0 DMA Queue Number Register 0 (Channels 00 to 07)
0x01C0 0244 DMAQNUM1 DMA Queue Number Register 1 (Channels 08 to 15)
0x01C0 0248 DMAQNUM2 DMA Queue Number Register 2 (Channels 16 to 23)
0x01C0 024C DMAQNUM3 DMA Queue Number Register 3 (Channels 24 to 31)
0x01C0 0250 DMAQNUM4 DMA Queue Number Register 4 (Channels 32 to 39)
0x01C0 0254 DMAQNUM5 DMA Queue Number Register 5 (Channels 40 to 47)
0x01C0 0258 DMAQNUM6 DMA Queue Number Register 6 (Channels 48 to 55)
0x01C0 025C DMAQNUM7 DMA Queue Number Register 7 (Channels 56 to 63)
0x01C0 0260 QDMAQNUM CC QDMA Queue Number
0x01C0 0264 - 0x01C0 0283 – Reserved
0x01C0 0284 QUEPRI Queue Priority Register
0x01C0 0288 - 0x01C0 02FF – Reserved
166 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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