Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-15. DM6467T EDMA Channel Synchronization Events
(1)
(continued)
EDMA
EVENT NAME EVENT DESCRIPTION
CHANNEL
4 AXEVTE0 McASP0 Transmit Event Even
5 AXEVTO0 McASP0 Transmit Event Odd
6 AXEVT0 McASP0 Transmit Event
7 AREVTE0 McASP0 Receive Event Even
8 AREVTO0 McASP0 Receive Event Odd
9 AREVT0 McASP0 Receive Event
10 AXEVTE1 McASP1 Transmit Event Even
11 AXEVTO1 McASP1 Transmit Event Odd
12 AXEVT1 McASP1 Transmit Event
13-15 – Reserved
16 SPIXEVT SPI Transmit Event
17 SPIREVT SPI Receive Event
18 URXEVT0 UART 0 Receive Event
19 UTXEVT0 UART 0 Transmit Event
20 URXEVT1 UART 1 Receive Event
21 UTXEVT1 UART 1 Transmit Event
22 URXEVT2 UART 2 Receive Event
23 UTXEVT2 UART 2 Transmit Event
24-27 – Reserved
28 ICREVT I2C Receive Event
29 ICXEVT I2C Transmit Event
30-31 – Reserved [Unused]
32 GPINT0 GPIO 0 Interrupt Event
33 GPINT1 GPIO 1 Interrupt Event
34 GPINT2 GPIO 2 Interrupt Event
35 GPINT3 GPIO 3 Interrupt Event
36 GPINT4 GPIO 4 Interrupt Event
37 GPINT5 GPIO 5 Interrupt Event
38 GPINT6 GPIO 6 Interrupt Event
39 GPINT7 GPIO 7 Interrupt Event
40 GPBNKINT0 GPIO Bank 0 Interrupt Event
41 GPBNKINT1 GPIO Bank 1 Interrupt Event
42 GPBNKINT2 GPIO Bank 2 Interrupt Event
43 CP_ECDCMP1 HDVICP1 ECDCMP Interrupt Event
44 CP_MC1 HDVICP1 MC Interrupt Event
45 CP_BS1 HDVICP1 BS Interrupt Event
46 CP_CALC1 HDVICP1 CALC Interrupt Event
47 CP_LPF1 HDVICP1 LPF Interrupt Event
48 TEVTL0 Timer 0 Event Low Interrupt
49 TEVTH0 Timer 0 Event High Interrupt
50 TEVTL1 Timer 1 Event Low Interrupt
51 TEVTH1 Timer 1 Event High Interrupt
52 PWM0 PWM 0 Interrupt Event
53 PWM1 PWM 1 Interrupt Event
54-56 – Reserved
57 CP_ME0 HDVICP0 ME Interrupt Event
58 CP_IPE0 HDVICP0 IPE Interrupt Event
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 163
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