Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
7.6 Enhanced Direct Memory Access (EDMA3) Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the DM6467T device. These data transfers include cache servicing, non-cacheable memory accesses,
user-programmed data transfers, and host accesses. These are summarized as follows:
• Transfer to/from on-chip memories
– ARM926 TCM
– DSP L1D memory
– DSP L2 memory
• Transfer to/from external storage
– DDR2 SDRAM
– NAND flash
– Asynchronous EMIF (EMIFA)
– ATA
• Transfer to/from peripherals/hosts
– VLYNQ
– HPI
– McASP0/1
– SPI
– I2C
– PWM0/1
– UART0/1/2
– PCI
The EDMA supports two addressing modes: constant addressing and increment addressing. On the
DM6467T, constant addressing mode is not supported by any peripheral or internal memory. For more
information on these two addressing modes, see the TMS320DM646x DMSoC Enhanced Direct Memory
Access (EDMA) Controller User’s Guide (literature number SPRUEQ5).
The DM6467T device supports a programmable default burst size feature. The default burst size of each
EDMA3 Transfer Controller (TC) is configured via the EDMA Transfer Controller Default Burst Size
Configuration register (EDMATCCFG). For more detailed information on the EDMATCCFG register, see
Section 4.6.2, Peripheral Selection After Device Reset.
7.6.1 EDMA3 Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 7-15 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM6467T device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the TMS320DM646x DMSoC Enhanced
Direct Memory Access (EDMA) Controller User’s Guide (literature number SPRUEQ5)
Table 7-15. DM6467T EDMA Channel Synchronization Events
(1)
EDMA
EVENT NAME EVENT DESCRIPTION
CHANNEL
0-3 – Reserved
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with
the transfer completion or alternate transfer completion events. For more detailed information on
EDMA event-transfer chaining, see the TMS320DM646x DMSoC Enhanced Direct Memory Access
(EDMA) Controller User's Guide (literature number SPRUEQ5).
162 Peripheral Information and Electrical Specifications Copyright © 2009–2012, Texas Instruments Incorporated
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