Datasheet

DEV_MXI/
DEV_CLKIN
2
3
4
4
5
1
1
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.5.5 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 7-12. Timing Requirements for DEV_MXI/DEV_CLKIN
(1) (2) (3) (4)
(see Figure 7-15)
-1G
NO. UNIT
MIN NOM MAX
1 t
c(DMXI)
Cycle time, DEV_MXI/DEV_CLKIN 28.57 30.03 50 ns
2 t
w(DMXIH)
Pulse duration, DEV_MXI/DEV_CLKIN high 0.45C 0.55C ns
3 t
w(DMXIL)
Pulse duration, DEV_MXI/DEV_CLKIN low 0.45C 0.55C ns
4 t
t(DMXI)
Transition time, DEV_MXI/DEV_CLKIN 7 ns
5 t
J(DMXI)
Period jitter, DEV_MXI/DEV_CLKIN 0.02C ns
(1) The DEV_MXI/DEV_CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the
specific range for CPU operating frequency. For example, for a -1G speed device with a 33.3-MHz DEV_CLKIN frequency, the PLL
multiply factor should be ≤ 30.
(2) The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
(3) For more details on the PLL multiplier factors, see the TMS320DM646x DMSoC ARM Subsystem Reference Guide (Literature Number
SPRUEP9).
(4) C = DEV_CLKIN cycle time in ns. For example, when DEV_MXI/DEV_CLKIN frequency is 33.3 MHz, use C = 30.03 ns.
Figure 7-15. DEV_MXI/DEV_CLKIN Timing
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 159
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