Datasheet

DM646x
PLL2V
DD18
C2
C1
EMIFilter
+1.8V
0.01 Fμ
PLL2
0.1 Fμ
C4
C3
EMIFilter
+1.8V
0.01 Fμ
PLL1
0.1 Fμ
PLL1V
DD18
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.5 Clock PLLs
There are two independently controlled PLLs on DM6467T. PLL1 generates the frequencies required for
the ARM, DSP, HDVICP0/1, EDMA, and peripherals. PLL2 generates the frequencies required for the
DDR2 interface. Any input crystal frequency between 27 MHz and 35 MHz can be used for the System
Oscillator (DEV_MXI/DEV_CLKIN). The recommended reference clock for both PLLs is the 33-MHz or
33.3-MHz crystal input. The DM6467T has a third PLL that is embedded within the USB2.0 PHY and the
24-MHz oscillator is its reference clock source. This particular PLL is only usable for USB operation, and is
discussed further in the TMS320DM646x DMSoC Universal Serial Bus (USB) Controller User's Guide
(literature number SPRUER7).
7.5.1 PLL1 and PLL2
Both PLL1 and PLL2 power are supplied externally via the 1.8-V PLL power-supply pins (PLL1V
DD18
and
PLL2V
DD18
). An external EMI filter circuit must be added to PLL1V
DD18
and PLL2V
DD18
, as shown in
Figure 7-11. The 1.8-V supply of the EMI filters must be from the same 1.8-V power plane supplying the
device’s 1.8-V I/O power-supply pins (DV
DDR2
). TI recommends EMI filter manufacturer Murata, part
number NFM18CC222R1C3.
All PLL external components (C1, C2, C3, C4, and the EMI Filters) must be placed as close to the device
as possible. For the best performance, TI recommends that all the PLL external components be on a
single side of the board without jumpers, switches, or components other than the ones shown in Figure 7-
11. For reduced PLL jitter, maximize the spacing between switching signals and the PLL external
components (C1, C2, C3, C4, and the EMI Filters).
Figure 7-11. PLL1 and PLL2 External Connection
The minimum CLKIN rise and fall times should also be observed. For the input clock timing requirements,
see Section 7.5.5, Clock PLL Electrical Data/Timing (Input and Output Clocks).
There is an allowable range for PLL multiplier (PLLM). There is a minimum and maximum operating
frequency for DEV_MXI/DEV_CLKIN, PLLOUT, AUX_MXI/AUX_CLKIN, and the device clocks
(SYSCLKs). The PLL Controllers must be configured not to exceed any of these constraints documented
in this section (certain combinations of external clock inputs, internal dividers, and PLL multiply ratios
might not be supported). For these constraints (ranges), see Table 7-7 through Table 7-9 .
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