Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information

TMS320DM6467T
www.ti.com
SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-4. PSC Registers (continued)
REGISTER
HEX ADDRESS RANGE DESCRIPTION
ACRONYM
0x01C4 1874 MDSTAT29 Module Status 29 Register (PWM0)
0x01C4 1878 MDSTAT30 Module Status 30 Register (PWM1)
0x01C4 187C MDSTAT31 Module Status 31 Register (I2C)
0x01C4 1880 MDSTAT32 Module Status 32 Register (SPI)
0x01C4 1884 MDSTAT33 Module Status 33 Register (GPIO)
0x01C4 1888 MDSTAT34 Module Status 34 Register (TIMER0)
0x01C4 188C MDSTAT35 Module Status 35 Register (TIMER1)
0x01C4 1890 - 0x01C4 18B3 – Reserved
0x01C4 18B4 MDSTAT45 Module Status 45 Register (ARM INTC)
0x01C4 18B8 - 0x01C4 19FF – Reserved
0x01C4 1A00 - 0x01C4 1A03 – Reserved
0x01C4 1A04 MDCTL1 Module Control 1 Register (C64x+ CPU)
0x01C4 1A08 MDCTL2 Module Control 2 Register (HDVICP0)
0x01C4 1A0C MDCTL3 Module Control 3 Register (HDVICP1)
0x01C4 1A10 MDCTL4 Module Control 4 Register (EDMA CC)
0x01C4 1A14 MDCTL5 Module Control 5 Register (EDMA TC0)
0x01C4 1A18 MDCTL6 Module Control 6 Register (EDMA TC1)
0x01C4 1A1C MDCTL7 Module Control 7 Register (EDMA TC2)
0x01C4 1A20 MDCTL8 Module Control 8 Register (EDMA TC3)
0x01C4 1A24 MDCTL9 Module Control 9 Register (USB)
0x01C4 1A28 MDCTL10 Module Control 10 Register (ATA)
0x01C4 1A2C MDCTL11 Module Control 11 Register (VLYNQ)
0x01C4 1A30 MDCTL12 Module Control 12 Register (HPI)
0x01C4 1A34 MDCTL13 Module Control 13 Register (PCI)
0x01C4 1A38 MDCTL14 Module Control 14 Register (EMAC)
0x01C4 1A3C MDCTL15 Module Control 15 Register (VDCE)
0x01C4 1A40 MDCTL16 Module Control 16 Register (Video Port)
0x01C4 1A44 MDCTL17 Module Control 17 Register (Video Port)
0x01C4 1A48 MDCTL18 Module Control 18 Register (TSIF0)
0x01C4 1A4C MDCTL19 Module Control 19 Register (TSIF1)
0x01C4 1A50 MDCTL20 Module Control 20 Register (DDR2 Mem Ctlr)
0x01C4 1A54 MDCTL21 Module Control 21 Register (EMIFA)
0x01C4 1A58 MDCTL22 Module Control 22 Register (McASP0)
0x01C4 1A5C MDCTL23 Module Control 23 Register (McASP1)
0x01C4 1A60 MDCTL24 Module Control 24 Register (CRGEN0)
0x01C4 1A64 MDCTL25 Module Control 25 Register (CRGEN1)
0x01C4 1A68 MDCTL26 Module Control 26 Register (UART0)
0x01C4 1A6C MDCTL27 Module Control 27 Register (UART1)
0x01C4 1A70 MDCTL28 Module Control 28 Register (UART2)
0x01C4 1A74 MDCTL29 Module Control 29 Register (PWM0)
0x01C4 1A78 MDCTL30 Module Control 30 Register (PWM1)
0x01C4 1A7C MDCTL31 Module Control 31 Register (I2C)
0x01C4 1A80 MDCTL32 Module Control 32 Register (SPI)
0x01C4 1A84 MDCTL33 Module Control 33 Register (GPIO)
0x01C4 1A88 MDCTL34 Module Control 34 Register (TIMER0)
0x01C4 1A8C MDCTL35 Module Control 35 Register (TIMER1)
0x01C4 1A90 - 0x01C4 1AB3 – Reserved
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