Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
Table 7-2. DM6467T Clock Domains
CLOCK DOMAIN CLOCK FIXED RATIO vs.
CLOCK MODES FREQUENCY (MHz)
DOMAIN SOURCE SYSCLK1 FREQ
SUBSYSTEM
BYPASS MODE
PLL MODE (-1G)
(1)
[default RATIO]
DSP Subsystem PLLDIV1 PLLC1 SYSCLK1 1:1 33.30 MHz 999 MHz
ARM926 Subsystem, 1:2
EDMA3, HDVICP, PCI,
PLLDIV2 PLLC1 SYSCLK2 16.65 MHz 499.50 MHz
VDCE, VPIF, TSIFs, DDR2
Mem Ctlr
Peripherals (GPIO, Timers, 1:4
I2C, PWMs, HPI, EMAC,
EMIFA, VLYNQ, SPI, ARM
PLLDIV3 PLLC1 SYSCLK3 8.33 MHz 249.75 MHz
INTC, USB2.0, UARTs,
McASPs, CRGENs,
SYSTEM)
ATA 1:6 [default]
PLLDIV4 PLLC1 SYSCLK4 5.55 MHz 142.71 MHz
1:7
(2)
TSIF0
(3)
1:8 [default]
PLLDIV5 PLLC1 SYSCLK5 4.16 MHz 99.90 MHz
1:10
(2)
TSIF1
(3)
1:8 [default]
PLLDIV6 PLLC1 SYSCLK6 4.16 MHz 99.90 MHz
1:10
(2)
VPIF
(3)
1:8 [default]
PLLDIV8 PLLC1 SYSCLK8 4.16 MHz 142.71 MHz
(4)
1:7
(2)
VLYNQ 1:6 [default]
PLLDIV9 PLLC1 SYSCLK9 5.55 MHz 99.90 MHz
1:10
(2)
DDR2 PHY PLLDIV1 PLLC2 SYSCLK1 1:1 33.30 MHz 799.20 MHz
(1) These table values assume a DEV_MXI/DEV_CLKIN of 33.3 MHz and a PLL1 multiplier equal to 30. Any input crystal with a frequency
between 20 MHz and 35 MHz can be used.
(2) To achieve these quoted frequencines, the PLLC1 SYSCLKx (for SYSCLK4, SYSCLK5, SYSCLK6, SYSCLK8, SYSCLK9) default
divider values must be changed based on the input crystal frequency. For the steps to change the PLLC1 SYSCLKx divider values, see
theTMS320DM646x DMSoC ARM Subsystem Reference Guide (literature number SPRUEP9).
(3) These domain clock sources, along with VP_CLKIN[3:0], STC_CLKIN, CRG0_VCXI, and CRG1_VCXI clock signals, go through the
clock select logic to determine the clock source enabled as the input to the VPIF and TSIF peripherals.
(4) Use an external clock source for the 54-/74.25-/108-/148.5-MHz VPIF clock.
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 143
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