Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7.3 Power Supplies
For more information regarding TI's power management products and suggested devices to power TI
DSPs, visit www.ti.com/processorpower.
7.3.1 Power-Supply Sequencing
The DM6467T includes one core supply (CV
DD
), and two I/O supplies—DV
DD33
and DV
DDR2
. To ensure
proper device operation, a specific power-up sequence must be followed. Some TI power-supply devices
include features that facilitate power sequencing—for example, Auto-Track and Slow-Start/Enable
features. For more information on TI power supplies and their features, visit www.ti.com/processorpower.
Here is a summary of the power sequencing requirements:
• The power ramp order must be CV
DD
before DV
DDR2
, and DV
DDR2
before DV
DD33
—meaning during
power up, the voltage at the DV
DDR2
rail should never exceed the voltage at the CV
DD
rail. Similarly,
the voltage at the DV
DDD33
rail should never exceed the voltage at the DV
DDR2
rail.
• From the time that power ramp begins, all power supplies (CV
DD
, DV
DDR2
, DV
DD33
) must be stable
within 200 ms. The term "stable" means reaching the recommended operating condition (see
Section 6.2, Recommended Operating Conditions table).
7.3.2 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DSP (or DSP array) to minimize
inductance and resistance in the power delivery path. Additionally, when designing for high-performance
applications utilizing the DM6467T device, the PC board should include separate power planes for core,
I/O, and ground; all bypassed with high-quality low-ESL/ESR capacitors.
7.3.3 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DM6467T. These caps need to be close to the DM6467T power pins, no more than
1.25 cm maximum distance to be effective. Physically smaller caps, such as 0402, are better but need to
be evaluated from a yield/manufacturing point-of-view. Parasitic inductance limits the effectiveness of the
decoupling capacitors, therefore physically smaller capacitors should be used while maintaining the largest
available capacitance value.
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 μF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
As with the selection of any component, verification of capacitor availability over the product's production
lifetime should be considered.
For more details on capacitor usage and placement, see the Implementing DDR2 PCB Layout on the
TMS320DM646x DMSoC Application Report (literature number SPRAAM1A).
7.3.4 DM6467T Power and Clock Domains
The DM6467T includes one single power domain — the "Always On" power domain. The "Always On"
power domain is always on when the chip is on. The "Always On" domain is powered by the CV
DD
pins of
the DM6467T. All DM6467T modules lie within the "Always On" power domain. Table 7-1 provides a
listing of the DM6467T clock domains.
Two primary reference clocks are required for the DM6467T device. These can either be crystal inputs or
driven by external oscillators. A 33-MHz or 33.3-MHz crystal is recommended for the system PLLs, which
generate the internal clocks for the ARM926, DSP, HDVICPs, peripherals, and the EDMA3. A 24- or 48-
MHz crystal is also required if the USB (24-MHz only) or UART (either 24- or 48-MHz) peripherals are to
be used. In addition, the 24- or 48-MHz input clock can be used to source the McASPs' clocks. For further
description of the DM6467T clock domains, see Table 7-2 and Figure 7-4.
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 141
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