Datasheet

V =V MAX(orV MAX)
ref IL OL
V =V MIN(orV MIN)
ref IH OH
V
ref
TransmissionLine
4.0pF 1.85pF
Z0=50
(seeNote)
Ω
TesterPinElectronics
DataSheetTimingReferencePoint
Output
Under
Test
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
42 Ω 3.5nH
DevicePin
(seeNote)
TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
7 Peripheral Information and Electrical Specifications
7.1 Parameter Information
Figure 7-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
7.1.1 1.8-V and 3.3-V Signal Transition Levels
All input and output timing parameters are referenced to V
ref
for both "0" and "1" logic levels. For 3.3-V I/O,
V
ref
= 1.5 V. For 1.8-V I/O, V
ref
= 0.9 V.
Figure 7-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to V
IL
MAX and V
IH
MIN for input clocks, V
OL
MAX and V
OH
MIN for output clocks.
Figure 7-3. Rise and Fall Transition Time Voltage Reference Levels
7.1.2 3.3-V Signal Transition Rates
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
Copyright © 2009–2012, Texas Instruments Incorporated Peripheral Information and Electrical Specifications 139
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