Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
Low/full speed: USB_DN and USB_DP 2.8 USB_V
DDA3P3
V
High speed: USB_DN and USB_DP 360 440 mV
High-level output voltage (3.3V I/O except
V
OH
DV
DD33
= MIN, I
OH
= MAX 2.4 V
PCI-capable and I2C pins)
High-level output voltage (3.3V I/O PCI-
I
OH
= –0.5 mA, DV
DD33
= 3.3 V 0.9DV
DD33
(2)
V
capable pins)
Low/full speed: USB_DN and USB_DP 0.0 0.3 V
High speed: USB_DN and USB_DP –10 10 mV
Low-level output voltage (3.3V I/O except
DV
DD33
= MIN, I
OL
= MAX 0.4 V
V
OL
PCI-capable and I2C pins)
Low-level output voltage (3.3V I/O PCI-
I
OL
= 1.5 mA, DV
DD33
= 3.3 V 0.1DV
DD33
(2)
V
capable pins)
Low-level output voltage (3.3V I/O I2C pins) I
O
= 3 mA 0 0.4 V
V
LDO
USB_V
DDA1P2LDO
output voltage 1.14 1.2 1.26 V
V
I
= V
SS
to DV
DD33
without opposing
±20 μA
internal resistor
Input current [DC] (except I2C and PCI- V
I
= V
SS
to DV
DD33
with opposing
50 100 250 μA
capable pins) internal pullup resistor
(4)
V
I
= V
SS
to DV
DD33
with opposing
–250 –100 –50 μA
internal pulldown resistor
(4)
I
I
(3)
Input current [DC] (I2C) V
I
= V
SS
to DV
DD33
±20 μA
0 < V
I
< DV
DD33
= 3.3 V without
±50 μA
opposing internal resistor
0 < V
I
< DV
DD33
= 3.3 V with opposing
Input current (PCI-capable pins) [DC]
(5)
50 250 μA
internal pullup resistor
(4)
0 < V
I
< DV
DD33
= 3.3 V with opposing
–250 –50 μA
internal pulldown resistor
(4)
GMTCLK, MTXD[7:0], MTXEN –8 mA
DDR2; V
OH
= DV
DDR2
– 0.4 V –8 mA
I
OH
High-level output current [DC]
PCI-capable pins
–0.5
(2)
mA
(PCI pin function only)
All other peripherals –4 mA
GMTCLK, MTXD[7:0], MTXEN 8 mA
DDR2; V
OL
= 0.4 V 8 mA
I
OL
Low-level output current [DC]
PCI-capable pins
1.5
(2)
mA
(PCI pin function only)
All other peripherals 4 mA
V
O
= DV
DD33
or V
SS
; internal pull
±20 μA
disabled
I
OZ
(6)
I/O Off-state output current
V
O
= DV
DD33
or V
SS
; internal pull
±100 μA
enabled
CV
DD
= 1.3 V, DSP clock = 1 GHz
Core (CV
DD
, DEV_CV
DD
, AUX_CV
DD
)
I
CDD
ARM Clock = 500 MHz, DDR Clock = 1792.22 mA
supply current
(7)
400 MHz
DV
DD
= 3.3 V, DSP clock = 1 GHz
3.3V I/O (DV
DD33
, USB_V
DDA3P3
) supply
I
DDD
ARM Clock = 500 MHz, DDR Clock = 25.66 mA
current
(7)
400 MHz
(1) For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table.
(2) These rated numbers are from the PCI Local Bus Specification Revision 2.3. The DC specifications and AC specifications are defined in
Table 4-3 (DC Specifications for 3.3V Signaling) and Table 4-4 (AC Specifications for 3.3V Signaling), respectively.
(3) I
I
applies to input-only pins and bi-directional pins. For input-only pins, I
I
indicates the input leakage current. For bi-directional pins, I
I
indicates the input leakage current and off-state (Hi-Z) output leakage current.
(4) Applies only to pins with an internal pullup (IPU) or pulldown (IPD) resistor.
(5) PCI input leakage currents include Hi-Z output leakage for all bidirectional buffers with 3-state outputs.
(6) I
OZ
applies to output-only pins, indicating off-state (Hi-Z) output leakage current.
(7) Measured under the following conditions: 60% DSP CPU utilization; ARM doing typical activity (peripheral configurations, other
housekeeping activities); DDR2 Memory Controller at 50% utilization, 50% writes, 32 bits, 50% bit switching at room temperature (25
°C). The actual current draw varies across manufacturing processes and is highly application-dependent. For more details on core and
I/O activity, as well as information relevant to board power supply design, see the TMS320DM6467T Power Consumption Summary
Application Report (literature number SPRAB64).
Copyright © 2009–2012, Texas Instruments Incorporated Device Operating Conditions 137
Submit Documentation Feedback
Product Folder Link(s): TMS320DM6467T