Datasheet
Table Of Contents
- 1 Digital Media System-on-Chip (DMSoC)
- Table of Contents
- 2 Revision History
- 3 Device Overview
- 3.1 Device Characteristics
- 3.2 Device Compatibility
- 3.3 ARM Subsystem
- 3.3.1 ARM926EJ-S RISC CPU
- 3.3.2 CP15
- 3.3.3 MMU
- 3.3.4 Caches and Write Buffer
- 3.3.5 Tightly Coupled Memory (TCM)
- 3.3.6 Advanced High-Performance Bus (AHB)
- 3.3.7 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
- 3.3.8 ARM Memory Mapping
- 3.3.9 Peripherals
- 3.3.10 PLL Controller (PLLC)
- 3.3.11 Power and Sleep Controller (PSC)
- 3.3.12 ARM Interrupt Controller (AINTC)
- 3.3.13 System Module
- 3.3.14 Power Management
- 3.4 DSP Subsystem
- 3.5 Memory Map Summary
- 3.6 Pin Assignments
- 3.7 Terminal Functions
- 3.8 Device Support
- 3.9 Documentation Support
- 3.10 Community Resources
- 4 Device Configurations
- 4.1 System Module Registers
- 4.2 Power Considerations
- 4.3 Clock Considerations
- 4.4 Boot Sequence
- 4.5 Configurations At Reset
- 4.6 Configurations After Reset
- 4.7 Multiplexed Pin Configurations
- 4.7.1 Pin Muxing Selection At Reset
- 4.7.2 Pin Muxing Selection After Reset
- 4.7.3 Pin Multiplexing Details
- 4.7.3.1 PCI, HPI, EMIFA, and ATA Pin Muxing
- 4.7.3.2 PWM Signal Muxing
- 4.7.3.3 TSIF0 Input Signal Muxing (Serial/Parallel)
- 4.7.3.4 TSIF0 Output Signal Muxing (Serial/Parallel)
- 4.7.3.5 TSIF1 Input Signal Muxing (Serial Only)
- 4.7.3.6 TSIF1 Output Signal Muxing (Serial Only)
- 4.7.3.7 CRGEN Signal Muxing
- 4.7.3.8 UART0 Pin Muxing
- 4.7.3.9 UART1 Pin Muxing
- 4.7.3.10 UART2 Pin Muxing
- 4.7.3.11 ARM/DSP Communications Interrupts
- 4.7.3.12 Emulation Control
- 4.8 Debugging Considerations
- 5 System Interconnect
- 6 Device Operating Conditions
- 7 Peripheral Information and Electrical Specifications
- 7.1 Parameter Information
- 7.2 Recommended Clock and Control Signal Transition Behavior
- 7.3 Power Supplies
- 7.4 External Clock Input From DEV_MXI/DEV_CLKIN and AUX_MXI/AUX_CLKIN Pins
- 7.5 Clock PLLs
- 7.6 Enhanced Direct Memory Access (EDMA3) Controller
- 7.7 Reset
- 7.8 Interrupts
- 7.9 External Memory Interface (EMIF)
- 7.10 DDR2 Memory Controller
- 7.10.1 DDR2 Memory Controller Electrical Data/Timing
- 7.10.2 DDR2 Interface
- 7.10.2.1 DDR2 Interface Schematic
- 7.10.2.2 Compatible JEDEC DDR2 Devices
- 7.10.2.3 PCB Stackup
- 7.10.2.4 Placement
- 7.10.2.5 DDR2 Keep Out Region
- 7.10.2.6 Bulk Bypass Capacitors
- 7.10.2.7 High-Speed Bypass Capacitors
- 7.10.2.8 Net Classes
- 7.10.2.9 DDR2 Signal Termination
- 7.10.2.10 VREF Routing
- 7.10.2.11 DDR2 CK and ADDR_CTRL Routing
- 7.11 Video Port Interface (VPIF)
- 7.12 Transport Stream Interface (TSIF)
- 7.13 Clock Recovery Generator (CRGEN)
- 7.14 Video Data Conversion Engine (VDCE)
- 7.15 Peripheral Component Interconnect (PCI)
- 7.16 Ethernet MAC (EMAC)
- 7.17 Management Data Input/Output (MDIO)
- 7.18 Host-Port Interface (HPI) Peripheral
- 7.19 USB 2.0 [see Note]
- 7.20 ATA Controller
- 7.21 VLYNQ
- 7.22 Multichannel Audio Serial Port (McASP0/1) Peripherals
- 7.23 Serial Peripheral Interface (SPI)
- 7.24 Universal Asynchronouse Receiver/Transmitter (UART)
- 7.25 Inter-Integrated Circuit (I2C)
- 7.26 Pulse Width Modulator (PWM)
- 7.27 Timers
- 7.28 General-Purpose Input/Output (GPIO)
- 7.29 IEEE 1149.1 JTAG
- 8 Mechanical Packaging and Orderable Information
TMS320DM6467T
SPRS605C –JULY 2009–REVISED JUNE 2012
www.ti.com
6.2 Recommended Operating Conditions
MIN NOM MAX UNIT
Supply voltage, Core (CV
DD
, DEV_CV
DD
,
CV
DD
(-1G) 1.235 1.3 1.365 V
AUX_CV
DD
)
(1)
Supply voltage, I/O, 3.3V (DV
DD33
, USB_V
DDA3P3
) 3.14 3.3 3.46 V
DV
DD
Supply voltage, I/O, 1.8V (DV
DDR2
, PLL1V
DD18
, PLL2V
DD18
,
1.71 1.8 1.89 V
DEV_DV
DD18
, AUX_DV
DD18
, USB_V
DD1P8
(2)
)
Supply ground (V
SS
, PLL1V
SS
, PLL2V
SS
, DEV_V
SS
(3)
,
V
SS
0 0 0 V
AUX_V
SS
(3)
, USB_V
SSREF
)
DDR_VREF DDR2 reference voltage
(4)
0.49DV
DDR2
0.5DV
DDR2
0.51DV
DDR2
V
DDR2 impedance control, connected via 50-Ω (±5%
DDR_ZP V
SS
V
tolerance) resistor to V
SS
DDR2 impedance control, connected via 50-Ω (±5%
DDR_ZN DV
DDR2
V
tolerance) resistor to DV
DDR2
High-level input voltage, 3.3 V (except JTAG[TCK], PCI-
2 V
capable, and I2C pins)
High-level input voltage, JTAG [TCK] 2.5 V
V
IH
High-level input voltage, PCI 0.5DV
DD33
V
High-level input voltage, I2C 0.7DV
DD33
V
High-level input voltage, non-DDR I/O, 1.8 V 0.65DV
DD18
V
Low-level input voltage, 3.3 V (except PCI-capable and I2C
0.8 V
pins)
Low-level input voltage, PCI 0.3DV
DD33
V
V
IL
Low-level input voltage, I2C 0 0.3DV
DD33
V
Low-level input voltage, non-DDR I/O, 1.8 V 0.35DV
DD18
V
Default 0 85 °C
T
c
Operating case temperature
D Version -40 85 °C
F
SYSCLK1
DSP Operating Frequency (SYSCLK1) -1G 20 1 GHz
(1) Future variants of TI SoC devices may operate at voltages ranging from 0.9 V to 1.4 V to provide a range of system power/performance
options. TI highly recommends that users design-in a supply that can handle multiple voltages within this range (i.e., 1.0 V, 1.05 V,
1.1 V, 1.14 V, 1.2 V, 1.26 V, 1.3 V, 1.365 V with ± 3% tolerances) by implementing simple board changes such as reference resistor
values or input pin configuration modifications. Not incorporating a flexible supply may limit the system's ability to easily adapt to future
versions of TI SoC devices.
(2) Oscillator 1.8 V power supply (DEV_DV
DD18
) can be connected to the same 1.8 V power supply as DV
DDR2
.
(3) Oscillator ground (DEV_V
SS
and AUX_V
SS
) must be kept separate from other grounds and connected directly to the crystal load
capacitor ground.
(4) DDR_VREF is expected to equal 0.5DV
DDR2
of the transmitting device and to track variations in the DV
DDR2
.
136 Device Operating Conditions Copyright © 2009–2012, Texas Instruments Incorporated
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