Datasheet

TMS320DM6467T
www.ti.com SPRS605C –JULY 2009–REVISED JUNE 2012
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0000 0000 0000 0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved INTNMI Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0
R-0000 000 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 4-21. DSPINTSET Register [0x01C4 0064]
Table 4-40. DSPINTSET Register Bit Descriptions
BIT NAME DESCRIPTION
31:9 Reserved Reserved. A read returns 0.
8 INTNMI DSP NMI Set
(1)
7:4 Reserved Reserved. A read returns 0.
3 INTDSP3 ARM-to-DSP Int3 Set
(1)
2 INTDSP2 ARM-to-DSP Int2 Set
(1)
1 INTDSP1 ARM-to-DSP Int1 Set
(1)
0 INTDSP0 ARM-to-DSP Int0 Set
(1)
(1) Writing a '1' generates the interrupt and sets the corresponding bit in the DSPINT status register. The register bit automatically clears to
a value of '0'. Writing a '0' has no effect. This register always reads as '0'.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0000 0000 0000 0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved INTNMI Reserved INTDSP3 INTDSP2 INTDSP1 INTDSP0
R-0000 000 R/W-0 R-0000 R/W-0 R/W-0 R/W-0 R/W-0
LEGEND: R = Read, W = Write, n = Value at reset
Figure 4-22. DSPINTCLR Register [0x01C4 0068]
Table 4-41. DSPINTCLR Register Bit Descriptions
BIT NAME DESCRIPTION
31:9 Reserved Reserved. A read returns 0.
8 INTNMI DSP NMI Clear
(1)
7:4 Reserved Reserved. A read returns 0.
3 INTDSP3 ARM-to-DSP Int3 Clear
(1)
2 INTDSP2 ARM-to-DSP Int2 Clear
(1)
1 INTDSP1 ARM-to-DSP Int1 Clear
(1)
0 INTDSP0 ARM-to-DSP Int0 Clear
(1)
(1) Writing a '1' clears the corresponding bit in the DSPINT status register. The register bit automatically clears to a value of '0'. Writing a '0'
has no effect. This register always reads as '0'.
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